Conductive-overlaid self-aligned MOS-gated semiconductor devices

Details Conductive-overlaid self-aligned MOS-gated semiconductor devices Conductive-overlaid self-aligned MOS-gated semiconductor devices

1995-03-22

1996-06-18

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257341, 257382, H01L 2976, H01L 2994, H01L 31062

Patent

active

055280633

ABSTRACT:
In a gated semiconductor device, a doped polysilicon layer overlies an insulated gate. The doped polysilicon layer extends over the top and the sidewalls of the gate to contact the underlying substrate. The dopants implanted in the polysilicon layer are diffused into the underlying substrate to form the source region in a self-aligned process which requires no extra masking step. The doped polysilicon layer, by contacting the source region and also overlying the gate, allows external electrical contact to be made directly to the doped polycrystalline silicon layer and to the surface of the substrate, eliminating the need for a special source contact adjacent to the gate. This conserves surface area of the device, allowing fabrication of a smaller and hence more economical device.

REFERENCES:
patent: 4375717 (1983-03-01), Tonnel
patent: 4417385 (1983-11-01), Temple
patent: 4598461 (1986-07-01), Love
patent: 5285094 (1994-02-01), Mori et al.

Affiliated with

Also associated with

Rating

Conductive-overlaid self-aligned MOS-gated semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Conductive-overlaid self-aligned MOS-gated semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Conductive-overlaid self-aligned MOS-gated semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-224791