Conductive interconnection for semiconductor integrated...

Details Conductive interconnection for semiconductor integrated... Conductive interconnection for semiconductor integrated...

1998-05-21

2001-02-20

Everhart, Caridad (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S128000, C438S129000, C438S622000, C438S586000

Reexamination Certificate

active

06191020

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor device fabrication. More particularly, the present invention relates to a conductive interconnection for semiconductor integrated circuit to eliminate the antenna effect while conductive layers are patterned by means of plasma etching processes, and its method of forming the same.
2. Description of the Prior Art
Referring to
FIG. 1A
, a perspective view of conductive interconnections for an integrated circuit is schematically depicted to explain the antenna effect when a metal layer is patterned by means of plasma etching processes. In the drawing, reference numeral
10
denotes a semiconductor substrate. Field oxides
12
are thermally grown on the substrate
10
and used to define an active region therebetween. A gate oxide layer
14
is formed to overlie the surface of the substrate
10
within the range of the active region. A polysilicon line
16
, doped with impurities to increase the conductivity thereof, is formed on the gate oxide layer
14
and extended onto the field oxide
12
for interconnection. The portion of the polysilicon layer
16
formed on the gate oxide layer
14
acts as the gate of a transistor. Reference numeral
18
designates metal lines, one of which is exemplified in FIG.
1
A.
In the drawing, the metal line
18
is connected to the polysilicon layer
16
through a contact window. As to the connection of two metal lines, a metal via is utilized instead of the contact window. Nevertheless, both of the contact window and the metal via are openings formed in insulating layers (not shown in the drawing), respectively. Consequently, the overlying layer is deposited on and fills in the associated opening to connect the underlying layer. The portion of the overlying layer filling in the associated opening is called a conductive plug because of its shape. For example, as shown in
FIG. 1A
, a conductive plug
20
is provided to electrically connect the metal line
18
to the polysilicon layer
16
.
In the manufacture of the high-density integrated circuits using multiple metal layer technology, electrical charges may build up at the device gate oxide during plasma etching processing. Plasma is a collection of charged particles, including electrons and positive or negative ions. Therefore, a plasma current density J
PLASMA
might be either positive or negative according to the polarity of the charged particles. Because there is a direct connection path between the metal line
18
and polysilicon line
16
, the charged particles accumulate on the metal line
18
during plasma etch processing flowing towards the gate oxide
14
. Therefore, the metal line
18
serves as a current receiver, which will amplify the charging effect. If the exposed area of the metal line
18
during plasma etch processing is large enough to trap the charged particles into the gate oxide and deteriorate the oxide quality; this phenomenon is called “antenna effect.”
In general, the larger the exposed metal area during plasma etching processing, the more charged particles will accumulate. The ratio of the exposed metal area to the gate oxide area is defined as an antenna ratio. When the antenna ratio exceeds a threshold value of, for example, about 200, an antenna current, designated as a current density J
F-N
in
FIG. 1A
, will be induced to flow through the gate oxide
14
due to Fowler-Nordheim tunneling and cause damage to the gate oxide
14
. Accordingly, this antenna effect can cause yield loss and reliability failures.
Referring to
FIG. 1B
, a diagram for expounding the antenna effect is schematically illustrated. In
FIG. 1B
, one device U
9
has an input terminal
22
a
standing for a node to be protected, hereinafter referred to as a protected node. As to semiconductor integrated circuit technology, the gate oxide is the most vulnerable to antenna damage, and the protected node
22
a
stands for the gate of a MOSFET (metal-oxide-semiconductor field-effect transistor) device under the circumstances. Another device U
10
has an output terminal
22
b
, which designates a node that does not need to be protected. Ma
1
and Ma
2
represent two first conductive lines formed from the same conductive layer for interconnection, which are connected to the protected node
22
a
and the node
22
b
, respectively. Va
1
represents a conductive plug. Moreover, Ma
3
represents a second conductive line that is electrically connected to the first conductive lines Ma
1
and Ma
2
through the respective conducting plugs Va
1
. Accordingly, the protected node
22
a
is electrically connected to the node
22
b.
In
FIG. 1B
, with conventional routing designs, it is impossible to assure that the length of the conductive lines Ma
1
, Ma
2
or Ma
3
is short enough to protect the protected node
22
a
from the antenna effect. Therefore, when the conductive layers are formed and patterned by means of plasma etch processing, the exposed area may be large enough to induce the antenna current J
F-N
flowing through the gate oxide and cause damage to the protected node
22
a.
Hence, two approaches have been proposed to protect the protected node from antenna damage while conductive layers are patterned by means of plasma etching processes.
One approach adds a P/N junction at the proximal end of the protected node
22
a
. The P/N junction has a breakdown voltage lower than that of the gate oxide. In other words, the P/N junction enters breakdown before the gate oxide so that it provides a path to discharge the induced antenna current, and therefore acts as a protection circuit for the protected node
22
a
while plasma etch processing is being applied.
The aforementioned first approach to avoid antenna damage is schematically depicted in
FIG. 2. A
diode D
1
constituted by a P/N junction is arranged on the path of the first conductive line Ma
1
. The diode D
1
has an anode and a cathode connected to ground and the first conductive line Ma
1
, respectively. The breakdown voltage of the diode D
1
is lower than that of the gate oxide. Accordingly, while induced during plasma etch processing, diode breakdown always precedes the gate oxide breakdown. Consequently, the induced antenna current can flow through the diode D
1
instead of flowing through the gate oxide and then discharge to ground.
However, as the semiconductor device is scaled down in size, the thickness of the gate oxide decreases and thus the breakdown voltage thereof linearly decreases. When the breakdown voltage for the gate oxide is lower than that of the diode D
1
, the diode D
1
is ineffectual and can not act as the protection circuit for the protected nodes
22
a
any more. Moreover, the addition of the diode D
1
increases layout area and process complexity.
The other approach takes antenna ratio into account so as to constrain the length of each conductive line coupled to the protected node
22
a
, accordingly, Referring to
FIG. 3
, the second approach to avoid antenna damage is schematically depicted. First conductive lines M
2
a
and M
2
ai
, formed from the same metal layer, are connected to the node
22
b
and the protected node
22
a
, respectively. Second conductive lines M
2
b
and M
2
bi
, formed from the same metal layer, are connected to the first conductive lines M
2
a
and M
2
ai
by conducting plugs V
2
a
and V
2
ai
, respectively. A third conductive line M
2
c
is electrically connected to the second conductive lines M
2
b
and M
2
bi
by conducting plugs V
2
b
. In this approach, the associated length of the underlying conductive lines M
2
ai
and M
2
bi
is strictly limited by the antenna ratio prior to the formation of the top conductive line M
2
c.
However, the second approach heavily relies on the antenna ratio, and therefore each gate oxide area should be extracted for calculation. For very-large-scale integrated circuit, millions of devices are fabricated on a chip. If each gate oxide area should be extracted for calculation, it is difficult to handle such tremendous data. Currently, few of IC

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