Static information storage and retrieval – Read/write circuit – Precharge
Patent
1998-07-30
2000-08-22
Peikari, B. James
Static information storage and retrieval
Read/write circuit
Precharge
365222, 365227, G06F 1216
Patent
active
061082554
ABSTRACT:
A novel SRAM construction allows for reduced power consumption by conditionally restoring only those memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines). In an alternative embodiment, a conditional restore circuit is used which selects the bit line based on data fed back to the precharge circuit from the output of the evaluated memory cell.
REFERENCES:
patent: 4241425 (1980-12-01), Cenker et al.
patent: 4817057 (1989-03-01), Kondo et al.
patent: 5748560 (1998-05-01), Sawada
patent: 5848015 (1998-12-01), Seno
Ciraula Michael Kevin
Lattimore George McNeil
Yeung Gus Wai-Yan
England Anthony V.S.
International Business Machines - Corporation
Peikari B. James
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