Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-11-30
2001-11-13
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000
Reexamination Certificate
active
06317804
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to integrated circuit device design and architecture, and in particular, to an interface for interconnecting multiple functional blocks together in an integrated circuit device.
BACKGROUND OF THE INVENTION
Computer technology has advanced a great deal over the last several decades. Whereas computers once filled entire rooms, and were constructed using individually packaged transistors and/or vacuum tubes to perform different logical functions, innovations in semiconductor manufacturing techniques have enabled multiple transistors, or logic gates, to be integrated together on a single integrated circuit device, or “chip” to perform a greater number of logical functions. The size and number of logic gates that can be integrated together on a chip continues to improve, and whereas early chips had at most only a few hundred gates, more recent chips have been developed that incorporate more on the order of millions of gates. Furthermore, advances in integration have permitted designs that were at one time implemented using multiple chips to be implemented in a single chip.
As chip designs become more complex, however, the design and development process becomes more expensive and time consuming. To alleviate this difficulty, design tools have been developed that enable developers to build custom chips by assembling together smaller, generic components that perform basic functions required for the design. By using generic components, design time and effort are reduced, since circuits do not need to be designed gate by gate. Moreover, the components usually can be tested and optimized prior to assembly in a particular design, so that the testing effort placed on the developer of an overall design is substantially reduced.
The ability to integrate greater numbers of gates onto a chip has also permitted the complexity of the generic components used by design tools to increase. Whereas early generic components replicated basic functions such as multiplexers, registers, counters, etc., more advanced components typically replicate higher level functions such as that of microprocessors, memory controllers, communications interface controllers, etc. These more advanced components are referred to herein as functional blocks, insofar as they are configured to perform one or more high level functions in a design. Functional blocks typically are portable to the extent that they are reusable in different designs. Moreover, they are often autonomous, and thus capable of operating independently and concurrently with other components in a design.
One difficulty associated with the use of components such as functional blocks arises from the need for the various components in a design to communicate with and transfer information among one another. Each component typically has one or more interfaces defined therefor through which communication with other components, or with other devices external to a chip, is handled. These interfaces are typically interconnected with one another over an interconnect system such as a bus to support communication between the different components.
For example, one common manner of interconnecting multiple components is through the use of a multidrop bus. With a multi-drop bus, each component is coupled to a common set of lines, so that each component is capable of receiving every communication passed over the bus. Information passed over a bus is usually associated with a particular address or other identifier so that, only the component that is the target of the information actually receives and processes that information. The other components that are not targeted for the information ignore the information.
Typically, a bus is parallel, incorporating multiple lines so that multiple bits of information can be transmitted simultaneously. Moreover, both control information, used by one component to control the operation of another component, and data, representing the information being manipulated by the components, are typically sent over the same lines in the bus. For example, one bus architecture used in integrating multiple functional blocks in a chip is the Peripheral Component Interconnect (PCI) bus architecture, which is more conventionally used at the board level to interconnect a microprocessor with different peripheral devices in a computer.
However, bus-type interconnections suffer from a number of drawbacks that limit their usefulness in interconnecting multiple functional blocks in a chip. First, parallel bus architectures require a relatively large number of lines, or wires, to run between the various components connected to the bus. Routing wires between components can take up valuable space in a design and reduce the number of components that can fit into the design. Many parallel buses, for example, transmit data in 32- or 64-bit words, requiring at a minimum 32 or 64 lines to be routed to each component, not counting any additional control signals that may be required.
Second, typically only one component can transmit information over a parallel bus at a time. Therefore, other components that desire to transmit information typically must wait until that component is done transmitting its information, or in the alternative, each component must share the bus and transmit pieces of information one after another, which slows down the transmission rate for all components. Also, control information and data typically share the same lines in a parallel bus, and as a result, control operations that might otherwise be capable of being performed within a particular component without requiring access to the bus may have to wait until a data transmission, started prior to the desired control operation, is complete.
Third, the overall speed of a parallel bus may be limited, and thus limit the potential bandwidth of information that can be communicated between components. Bandwidth in a parallel bus is typically improved by increasing the width of the bus or increasing the clock speed of the bus. Increasing the width, however, adds additional lines to the bus, thus adding to the routing density of the design. Increasing the clock speed, on the other hand, may limit the number of components that can be attached to the bus, since the number of components can affect the amount of load and routing parasitics on the bus, each of which limits permissible clock speed.
Therefore, a significant need exists in the art for an improved manner of interconnecting components such as functional blocks and the like in an integrated circuit design, and in particular, for a manner of interconnecting components that is more flexible, compact, fast, reusable, and expandible than conventional designs.
SUMMARY OF THE INVENTION
The invention addresses these and other problems associated with the prior art by providing a circuit arrangement and method that interface multiple functional blocks within an integrated circuit device via a concurrent serial interconnect that is capable of routing separate serial command, data and clock signals between functional blocks in the device. A concurrent serial interconnect consistent with the invention utilizes a plurality of serial ports that are selectively coupled to one another by an interface controller to define one or more logical communication channels between two or more of the serial ports. The logical communication channels in essence function as point-to-point serial interconnections between functional blocks, so that direct communications between logically connected functional blocks can occur.
Through the use of serial interconnects, the number of lines required to be routed to and from individual functional blocks is reduced, thereby simplifying the integration of functional blocks into a design and reducing the routing congestion associated with inter-block communication. In addition, by communicating via separate serial command, data and clock signals, high speed data throughput can be supported. Furthermore, should more than one logical communication channel be supported by an i
Lehman Judson Alan
Levy Paul S.
Lefkowitz Sumati
Philips Semiconductors Inc.
Wood Herron & Evans L.L.P.
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