Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
2007-07-03
2007-07-03
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
Reexamination Certificate
active
09748785
ABSTRACT:
A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be “killed” later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.
REFERENCES:
patent: 4187539 (1980-02-01), Eaton
patent: 5404496 (1995-04-01), Burroughs et al.
patent: 5430862 (1995-07-01), Smith et al.
patent: 5442757 (1995-08-01), McFarland et al.
patent: 5544311 (1996-08-01), Harenberg et al.
patent: 5546599 (1996-08-01), Song
patent: 5564041 (1996-10-01), Matsui et al.
patent: 5627981 (1997-05-01), Adler et al.
patent: 5644703 (1997-07-01), Kurakazu et al.
patent: 5715440 (1998-02-01), Ohmura et al.
patent: 5717909 (1998-02-01), Nemirovsky et al.
patent: 5752013 (1998-05-01), Christensen et al.
patent: 5754839 (1998-05-01), Pardo et al.
patent: 5857094 (1999-01-01), Nemirovsky
patent: 6353883 (2002-03-01), Grochowski et al.
patent: 0 667 576 (1995-08-01), None
patent: 0 720 092 (1995-12-01), None
patent: 0810519 (1997-12-01), None
patent: 0 849 674 (1998-06-01), None
patent: 0 869 434 (1998-10-01), None
patent: 0 943 995 (1999-09-01), None
Hennessy and Patterson, “Computer Architecture—A Quantitative Approach, 2nd Edition,” 1996, p. 184.
Hennessy and Patterson, “Computer Architecture—A Quantitative Approach, 2ndEdition,” 1996, p. 180.
British Search Report from British priority application No. 9930586.4, filed Dec. 23, 1999.
Standard Search Report in connection with British counterpart of U.S. Appl. No 09/748,077.
Standard Search Report in connection with British counterpart of U.S. Appl. No. 09/748,762.
Standard Search Report in connection with British counterpart of U.S. Appl. No. 09/748,763.
Standard Search Report in connection with British counterpart of U.S. Appl. No. 10/021,269.
Cofler Andrew
Sename Isabelle
Wojcieszak Laurent
Chan Eddie
Huisman David J.
Jorgenson Lisa K.
Morris James H.
STMicroelectronics S.A.
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