Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-03
2001-08-21
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S057000, C710S107000, C710S056000, C711S149000, C709S227000
Reexamination Certificate
active
06279065
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory systems in personal computers, and more particularly, to the manner in which memory is accessed. Still more particularly, the invention relates to a computer system in which write transactions from the processor to memory can be optimized by transmitting the data from the processor earlier in the transaction.
2. Background of the Invention
Computer architectures generally include a plurality of devices interconnected by one or more buses. For example, conventional computer systems typically include a central processing unit (“CPU”) coupled through bridge logic to main memory. A CPU bus usually is provided to couple the CPU to the bridge logic and a memory bus is provided to couple the bridge logic to the main memory. A main memory controller typically is incorporated within the bridge logic to generate various control signals for accessing the main memory. An interface to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (“PCI”) bus, may also be included as a portion of the bridge logic. Examples of devices which can be coupled to the local expansion bus include network interface cards, video accelerators, audio cards, SCSI adapters and telephony cards, to name a few. An older-style expansion bus also may be supported through yet an additional bus interface to provide compatibility with earlier-version expansion bus adapters. Examples of such expansion buses include the Industry Standard Architectures (ISA) bus, the Extended Industry Standard Architecture (“EISA”) bus, and the Microchannel Architecture (MCA) bus. Various devices may be coupled to this second expansion bus including a fax/modem, sound card, keyboard, and mouse. An example of such a bridge logic is described in U.S. Pat. No. 5,634,073, assigned to the assignee of the present invention.
The bridge logic can link or interface the CPU bus, a peripheral bus such as a PCI bus, and the memory bus. In applications that are graphics intensive, a separate peripheral bus optimized for graphics related data transfers may be supported by the bridge logic. An example of such a bus is the Advanced Graphic Port (“AGP”) bus. The AGP bus is generally considered a high performance, component level interconnect bus optimized for three dimensional graphical display applications. As one skilled in the art will understand, the AGP bus is based on a set of performance extensions or enhancements to the PCI standard. In part, the AGP bus was developed in response to the increasing demands placed on memory bandwidths for three-dimensional renderings. With the advent of AGP, a graphics controller can be removed from the PCI bus (where it traditionally was located) to the AGP bus. AGP provides greater bandwidth for data transfer between a graphics accelerator and system memory than is possible with PCI or other conventional bus architectures. The increase in data rate provided by the AGP bus allows some of the three dimensional rendering data structures, such as textures, to be stored in main memory, reducing the cost of requiring large amounts of dedicated memory for the graphics accelerator or frame buffer.
An important consideration for computer system designers is performance. Increases in performance are obtained from several cooperating factors. First, increasing the operating speed (i.e., clock frequency) of the computer system enables the computer to do more operations per unit time. Of course providing microprocessors that operate with faster internal clock signals does little to increase performance unless the rest of the computer system experiences a similar increase in operating speed. For example, a processor may be capable of storing data (also referred to as “writing” data) in memory at extremely high speed. Unless the memory is capable of receiving the data at the same rate, however, the processor must slow down to the speed of the memory. Memory device manufacturers can help remedy this problem by providing faster memory devices. Thus, to provide a computer system with improved performance, computer designers must implement improvements at various levels of the computer system.
Another approach to improving computer performance is to implement faster techniques in the computer for processing data, writing data to memory, reading data from memory, and the like. Such improved techniques can be implemented in computer hardware often without requiring a significant increase in the raw operating speed of the hardware. Because such techniques perform their functions more quickly than previous techniques, the overall performance level of the computer is increased.
An important focal point for computer designers is the interaction between the processor (often referred to as a central processing unit or “CPU” for short) and the computer's main memory. Typically, main memory includes dynamic random access memory (“DRAM”) which functions as the working memory of the CPU. Over the past decade, CPU manufacturers have created processors with operating speeds that have increased at a faster rate than DRAM devices. Thus, processors currently are capable of writing data to and reading data from DRAM memory faster than the DRAM is capable of responding. One technique to correct this speed discrepancy problem between CPU's and DRAM devices has been to insert “wait states” into the CPU's operating cycles. A wait state is a pause during which the CPU hesitates before continuing with its transactions. Thus, the CPU effectively can be slowed down to a compatible speed with the DRAM device through the use of wait states. Memory technology, however, has improved to the point where wait states are not needed in every computer system. Nevertheless, improving the CPU to memory transaction time remains a design driver even for computer systems that do not require the use of wait states.
SUMMARY OF THE INVENTION
The deficiencies of the prior art described above are solved in large part by a computer system including a CPU, a memory device, and a bridge logic unit coupling together the CPU and the memory device. The bridge logic unit includes a CPU interface coupled to the CPU and a memory controller coupled to the memory device. A CPU-to-memory data queue couples the CPU interface to the memory controller and provides a temporary storage queue for data written by the CPU to the memory device.
The CPU-to-memory data queue preferably is organized as one or more rows (most preferably four rows) of data storage with each row storing one or more bytes of data More particularly, each row provides storage for 32 bytes of data organized as four quad words, with each quad word representing eight of the 32 bytes. The CPU may store one, two, or four quad words (or less than a quad word, referred to as a sub-quad word) of write data to the CPU-to-memory data queue. The bridge logic unit also includes a CPU-to-memory address queue for storing the memory addresses of the write data stored (“posted”) in the CPU-to-memory queue.
The memory device may comprise any type of memory device, such as conventional dynamic random access memory (DRAM) or synchronous DRAM (SDRAM). Most memory devices have specific steps to be followed before a write transaction can be completed. For example, a typical SDRAM write cycle usually includes an activation cycle, a write cycle, and a precharge cycle. Memory technologies typically require the “opening” of that portion (typically referred to as a “page” or “bank”) of memory to which the write data is targeted. In conventional DRAM devices, this step is typically necessary before the write data can actually be written to memory. For SDRAM devices this process is usually referred to as “activation.” After the data has been written, conventional and synchronous DRAM also require that the opened memory portion be closed upon occurrence of predetermined crit
Chin Kenneth T.
Coffee C. Kevin
Collins Michael J.
Johnson Jerome J.
Jones Phillip M.
Compaq Computer Corporation
Conley & Rose & Tayon P.C.
Harris Jonathan M.
Heim Michael F.
Lee Thomas
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