Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-03-13
2001-03-06
Wiley, David A. (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C713S324000
Reexamination Certificate
active
06199134
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to circuitry that forms a communications “bridge” between components in a personal computer system. Still more particularly, the present invention relates to a bridge logic that implements a procedure for completing transactions to target devices that are in a sleep mode, while notifying the master device that the target is asleep.
2. Background of the Invention
A personal computer system includes a number of components with specialized functions that cooperatively interact to produce the many effects available in modern computer systems. The ability of these various components to exchange data and other signals is vital to the successful operation of a computer system. One of the critical requirements in designing a new computer system is that all system components (including those that may be added to the system by a user) must be compatible. A component is compatible if it effectively communicates and transfers data without interfering or contending with the operation of other system components. Because modern computer systems are designed with components that operate with different protocols, the likelihood that components may not properly communicate is heightened. Compatibility between devices with different protocols is achieved, at least in part, with bridge logic devices. As the name implies, bridge logic devices provide a communications “bridge” between components and busses that operate according to different protocols. The present invention is directed to an improved bridge logic device.
Computer systems include components with different protocols because of the manner in which computers have evolved, and the desire to design new computers to be backwardly-compatible with prior designs. Early computer systems had relatively few components. As an example, some of the early computer systems included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components typically were coupled together using a network of address, data and control lines, commonly referred to as a “bus.” As computer technology evolved, it became common to connect additional peripheral devices to the computer through ports (such as a parallel port or a serial port), or by including the peripheral device on the main system circuit board (or “motherboard”) and connecting it to the system bus.
The computer operates by having data flow through the system, with modification of the data occurring frequently. Typically, the CPU controls most of the activities of the computer system. The CPU supervises data flow and is responsible for most of the high-level data modification in the computer. The CPU, therefore, is the “heart” of the system and receives signals from the peripheral devices, reads and writes data to memory, processes data, and generates signals controlling the peripheral devices.
Since the introduction of the first computer systems, computer technology has continued to evolve at a relatively rapid pace. New peripheral devices have been developed, and both processor speeds and the size of memory arrays have increased dramatically. In addition to the introduction of more powerful and faster processors, and the emergence of new and improved peripheral devices, there has been an increasing desire for a mobile computer that can be easily used in more than one location. Such computers have come to be known as laptop computers, because the user can literally operate these mobile computers on his or her lap if desired. In contrast to traditional desktop computers that might weigh in excess of 25 pounds, laptop computers typically weigh less than 10 pounds, including the monitor and all peripherals.
FIG. 1
shows a representative prior art laptop computer system that includes a CPU coupled to a bridge logic device via a CPU bus. The bridge logic device is sometimes referred to as a “North bridge” for no other reason than it often is depicted at the upper end of a computer system drawing. The North bridge also couples to the main memory array by a memory bus. The North bridge couples the CPU and memory to the peripheral devices in the system through a Peripheral Component Interconntect (“PCT”) bus or other expansion bus. Various components that understand PCI protocol may reside on the PCI bus, such as a graphics controller.
As noted above, it is desirable to design computer systems so that they are backwardly compatible with prior peripheral designs. This backwards compatibility can be achieved by adding additional or secondary expansion busses that couple to the primary expansion bus. If other secondary expansion busses are provided in the computer system, another bridge logic device typically is used to couple the primary expansion bus to the secondary expansion bus. This bridge logic is sometimes referred to as a “South bridge” reflecting its location vis-a-vis the North bridge in a typical computer system drawing. An example of such bridge logic is described in U.S. Pat. No. 5,634,073, assigned to Compaq Computer Corporation.
In
FIG. 1
, the South bridge couples the PCI bus to an ISA bus. Various ISA-compatible devices are shown coupled to the ISA bus. As one skilled in the art will understand, devices residing on the ISA bus may be targets for devices coupled to the PCI bus, including the CPU. Thus, even though the CPU is not directly connected to the ISA bus, it may still read and write data, or perform other operations, to devices on that bus. The PCI protocol permits devices residing on the PCI to run master cycles to targets residing on the PCI bus.
Laptop computers have two critical design criteria that affect every component in the laptop computer. Those design criteria are size and power consumption. Laptops are designed to be as light and as thin as possible to make it easier for the user to carry. Thus, components are selected based, at least in part, on their size and weight. The second criteria, power consumption, reflects the fact that laptop computers are intended to operate at times solely upon battery power. Thus, the components used in a laptop are also selected based upon power consumption.
In an effort to extend the length of time that a laptop computer can operate under battery power, techniques have been developed that reduce power consumption when the system is not being used. Thus, for example, if a user has a laptop computer turned on, but is not actively inputting data into the system, the computer may automatically enter a low power mode to reduce power consumption. More recently, even more sophisticated techniques have been considered which permit particular components or peripheral devices to be placed in a low power (or sleep) mode. Thus, a laptop computer may cause a component, such as a hard drive, to go into a sleep mode independently of other system components if that drive has been inactive for a predetermined length of time. This flexibility can significantly reduce power consumption as selective system components are placed in a sleep mode even during periods when the user is using the system.
While this ability to independently place components in a sleep mode has obvious advantages, it also unfortunately has drawbacks. One serious drawback is that the components that are active may need to access components that are asleep. In that situation, there is a risk that a master device will complete a cycle to a sleeping target without realizing that the target was unable to properly process the transaction. Thus, data obtained during a read cycle to a sleeping target is likely invalid, and data that was to be written to a sleeping target may not have been accurately processed. Another risk is that the system may hang because the target does not provide the necessary signals back to pe
Deschepper Todd
Wunderlich Russ
Compaq Computer Corporation
Conley & Rose & Tayon P.C.
Harris Jonathan M.
Heim Michael F.
Wiley David A.
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