Computer system with a device for selectively blocking writeback

Details Computer system with a device for selectively blocking writeback Computer system with a device for selectively blocking writeback

1995-03-21

1997-09-02

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395872, 395873, G06F 1328

Patent

active

056641508

ABSTRACT:
A computer system that has a main memory and a writeback cache memory also has an I/O device capable of data streaming. A memory controller responds to signals that the I/O device will perform a burst transfer of data to the main memory and blocks potential writebacks from the cache memory to the I/O device. Potential writing over of the data from the I/O device by a flushed cache line written back to the main memory is thereby prevented. The system performance is increased since the data from the I/O device can be written to the main memory without waiting for a snoop cycle and a writeback to be performed.

REFERENCES:
patent: 4956768 (1990-09-01), Sidi et al.
patent: 5163132 (1992-11-01), DuLac et al.
patent: 5396597 (1995-03-01), Bodin et al.
patent: 5551006 (1996-08-01), Kulkarni
patent: 5553266 (1996-09-01), Metzger et al.
patent: 5555398 (1996-09-01), Raman

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