Computer system with a debug facility for a pipelined...

Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...

Reexamination Certificate

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C717S134000

Reexamination Certificate

active

07441109

ABSTRACT:
A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

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