Computer system controlling memory clock signal and method...

Details Computer system controlling memory clock signal and method... Computer system controlling memory clock signal and method...

1999-10-18

2003-03-04

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S167000, C710S058000, C713S500000

Reexamination Certificate

active

06530001

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from my application entitled COMPUTER SYSTEM CONTROLLING MEMORY CLOCK SIGNAL AND METHOD FOR CONTROLLING THE SAME earlier filed with the Korean Industrial Property Office on Oct. 16, 1998 and there duly assigned Serial No. 43756/1998.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems generally, and, more particularly, to a computer system and process for controlling memory clock signals.
2. Related Art
A system bus of a computer system is an operational path where a central processing unit (i.e., a CPU), a memory, and peripheral devices transmit data to one another. For example, a 100 mega-Hertz system bus transmission speed means that data is transmitted at a speed of 100 mega-Hertz. Chipset manufacturing companies intending to improve system bus speed have indicated that the current 66 MHz system bus transmission speed (often refer to as “PC
66
”) can not keep up with the increasing speed of the newer generations of central processing units.
Recent efforts in the art include U.S. Pat. No. 5,680,595 to Thomann et al. entitled PROGRAMMABLE DATA PORT CLOCKING SYSTEM FOR CLOCKING A PLURALITY OF DATA PORTS WITH A PLURALITY OF CLOCKING SIGNALS IN AN ASYNCHRONOUS TRANSFER MODE SYSTEM, issued Oct. 21, 1997; U.S. Pat. No. 5,509,138 to Cash et al, entitled METHOD FOR DETERMINING SPEEDS OF MEMORY MODULES, issued on Apr. 16, 1996; U.S. Pat. No. 5,761,533 to Aldereguia et al., entitled COMPUTER SYSTEM WITH VARIED DATA TRANSFER SPEEDS BETWEEN SYSTEM COMPONENTS AND MEMORY, issued on Jun. 21, 1998; U.S. Pat. No. 5,862,368 to Miller et al., entitled PROCESS TO ALLOW AUTOMATIC MICROPROCESSOR CLOCK FREQUENCY DETECTION AND SELECTION, issued on Jan. 19, 1999, U.S. Pat. No. 5,887,146 to Baxteretal., entitled SYMMETRIC MULTIPROCESSING COMPUTER WITH NON-UNIFORM MEMORY ACCESS ARCHITECTURE, issued on Mar. 23, 1999; U.S. Pat. No. 5,903,747 to Casal, entitled MICROPROCESSOR CLOCKING CONTROL SYSTEM, issued on May 11, 1999; U.S. Pat. No. 5,903,916 to Pawlowski et al., entitled COMPUTER MEMORY SUBSYSTEM AND METHOD FOR PERFORMING OPPORTUNISTIC WRITE DATA TRANSFERS DURING AN ACCESS LATENCY PERIOD WITHIN A READ OR REFRESH OPERATION, issued on May 11, 1999; and U.S. Pat. No. 5,522,064 to Aldereguia et al., entitled DATA PROCESSING APPARATUS FOR DYNAMICALLY SETTING TIMING IN A DYNAMIC MEMORY SYSTEM, issued on May 28, 1996. The efforts proposed by these references are, in my opinion, unsatisfactory. Aldereguia et al, U.S. Pat. No. 5,522,064 for example, proposes to use a programmable memory controller to store information that defines the timing requirements of each of the modules.
In an effort to address the perceived need for a system bus with a transmission speed that is more compatible with the newer microprocessors, Intel Corporation has developed a 100 MHz system bus transmission speed (often referred to below as “PC
100
”) in response to the fast developing speed of a CPU. That is, the PC
100
has a system bus transmission speed that is able to operate at 100 MHz. For example, the PC
100
can be used in a main board having with an Intel 440BX chipset driven by a high speed CPU such as a Pentium II microprocessor operating at 350 MHz.
The PC
100
system bus has two significant advantages. The first advantage is an improvement in system performance. For example, the operational time of a 66 MHz system bus is 66·10
5
/seconds. With the PC
100
system bus, 64 bits are operated upon at one time and 8 bits are equal to 1 byte, 528 MB/second may be transmitted via the PC
66
system bus. On the other hand, the operation time of a 100 MHz system bus is 10
8
/seconds. Thus, 800 MB/sec is transmitted via the PC
100
system bus, an improvement of data transmission speed of 51%.
The second advantage is the stability of peripheral devices that are used in conjunction with a PC
100
system bus. Since the processing speed of the 66 MHz system bus is too fast, a peripheral component interconnection bus (i.e., a PCI bus) is operated at 33 MHz/sec. Therefore, peripheral devices such as a graphic card and a hard disk drive are operated at 33 MHz. If a PC
66
system bus is converted by overclocking the bus from 66 MHz to 100 MHz, the PCI bus will be operated at 37.5 MHz (i. e., 13% over PCI limitations). Therefore, operational and functional errors such as shutdown may be generated by the overclocking of the PC
66
system bus. With a PC
100
system bus however, the PCI bus is operated at ⅓ of the clock speed (i.e., at 33.3 mega-Hertz), so that 33.3 MHz operational frequency of the PCI bus meets the PCI standard. Despite the use of a high system bus clock, high speed peripheral devices can still be stably used. Moreover, the 100 MHz system bus will be able to accommodate a high speed CPU of the next generation of microprocessors.
Despite these efforts in the art, I have found that it is conventional practice to either continuously supply clock signals to vacant memory module sockets or, when the memory clock signal to an unoccupied dual in line memory module socket is terminated, the unused memory clock signals are continuously supplied to the memory modules mounted in the occupied sockets. Consequently, computer systems subjected to conventional clock signal protocol are often unnecessarily exposed to electromagnetic interference (i.e., EMI). Thomann, U.S. Pat. No. 5,680,595, in an effort to provide a programmable data port clocking system, for example, relies upon mode storage to supply the setting data for a memory module, a mode decoder that decodes the setting data to provide a plurality of signals that correspond to a least one transfer mode, a mode controller that regulates the clock signal for the transfer mode that is output in response to the output signals, and a switching stage that outputs clock signals to a plurality of ports in response to the clock signal. Cash, U.S. Pat. No. 5,509,138, attempts to provide memory access in accordance with the different speeds of the memory modules, but requires the reading of the setting data defining the size, speed and composition code of the memory module, a decision about the position of data for the memory module, and the storage of the speed of the memory module whenever the memory module is included in the entry and the storage of a lowest speed for the memory module when that module is not included in the entry. These systems are not particularly simple and require more than a single operational cycle to implement.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved computer system.
It is another object to reduce the exposure of a computer system to electromagnetic interference.
It is still another object to provide a computer system and process able to terminate application of memory clock signals to vacant memory module sockets.
It is yet another object to provide a computer system and process able to terminate application of unnecessary memory clock signals to occupied memory module sockets.
It is still yet another object to provide a computer system and process able to automatically terminate the application of memory clock signals to an occupied memory module socket that do not conform to the bus speed of the memory module occupying that socket.
It is a further object to provide a computer system an process able to automatically adjust the application and frequency of the memory clock signals applied to each of a plurality of memory module sockets to conform to determinations of whether each socket is occupied, to determinations of the type of memory module that is resident within each socket, and to determinations of the bus speed of each memory module that is resident within each socket.
It is a still further object to implement a computer system and process that is able to cut off a clock signal to an unused memory module socket of a computer system and an unused clock signal among the clock signals being a

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