Computer system cache controller and methods of operation of...

Details Computer system cache controller and methods of operation of... Computer system cache controller and methods of operation of...

2006-12-12

2006-12-12

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C710S105000, C710S311000, C710S314000, C710S315000, C710S306000

Reexamination Certificate

active

07149848

ABSTRACT:
In at least some embodiments, a computer system comprises a central processing unit (“CPU”), a bridge device coupled to a main memory, and a cache controller coupled between the bridge device and the CPU. The computer system further comprises a cache memory coupled to the cache controller and providing memory space to the CPU, wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using a first protocol and the bridge device communicates using a second protocol, and wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using the second protocol and the bridge device communicates using the first protocol.

REFERENCES:
patent: 5860081 (1999-01-01), Herring et al.
Jeffrey D. Brown et al.; “IBM Enterprise X-Architecture Technology, Reaching the Summit,” 1st Edition 2002, International Business Machines, 158 pp.

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