Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent
1996-09-03
1999-07-27
Gossage, Glenn
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
711217, 371 211, 371 225, G06F 1200, G11C 2900
Patent
active
059308141
ABSTRACT:
A method and circuit are provided for generating a minimum-sized address filter to detect when the address space of an embedded memory having a smaller address space than another larger embedded memory is being exceeded. The method includes decomposing a maximum address into alternating sequences of consecutive binary ones (1's) and zeros (0's), discarding a final sequence if it contains binary 1's, and generating a filter circuit from a filter function formed from the alternating sequences of consecutive binary 1's and 0's. A built-in self test (BIST) circuit incorporating the address filter provides the ability to test a plurality of embedded memories at full speed in parallel. A computer system including a computer program for generating the filter circuit may also be provided.
REFERENCES:
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5258986 (1993-11-01), Zerbe
patent: 5535164 (1996-07-01), Adams et al.
patent: 5617531 (1997-04-01), Crouch et al.
Ghukasyan Hovhannes
Kraus Lawrence
Lepejian Yervant David
Marandjian Hrant
Credence Systems Corporation
Gossage Glenn
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