Composite gate electrode incorporating dopant diffusion-retardin

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438303, 438593, H01L 21336, H01L 213205

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058858776

ABSTRACT:
A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.

REFERENCES:
patent: 4369072 (1983-01-01), Bakeman, Jr. et al.
patent: 4420872 (1983-12-01), Solo De Zaldivar
patent: 4481527 (1984-11-01), Chen et al.
patent: 4575921 (1986-03-01), Bhagat
patent: 4597159 (1986-07-01), Usami et al.
patent: 4774197 (1988-09-01), Haddad et al.
patent: 4869781 (1989-09-01), Euen et al.
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 5518958 (1996-05-01), Giewont et al.
patent: 5567638 (1996-10-01), Lin et al.
patent: 5605848 (1997-02-01), Ngaoaram
Stanley Wolf, Silicon Processing for the VLSI Era, vol. 3: The Submicron MOSFET, Lattice Press, Sunset Beach, CA, 1995, pp. 305-313.
H. Sayama et al, "Low Voltage of Sub-Quarter Micron W-Polycide Dual Gate CMOS with Non-Uniformly Doped Channel," International Electron Devices Meeting Technical Digest, Dec. 8-11, 1996, San Francisco, CA, pp. 583-586.
C. T. Liu et al, "High Performance 0.2 .mu.m CMOS with 25 .ANG. Gate Oxide Grown on Nitrogen Implanted Si Subsstrates," International Electron Devices Meeting Technical Digest, San Francisco, CA, Dec. 8-11, 1996, pp. 499-502.
C.T. Liu et al., "25 .ANG. Gate Oxide without Boron Penetration for 0.25 and 0.3-.mu.m PMOSFETs," 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19.
Hattangady et al., "Ultrathin Nitrogen-Profile Engineered Gate Dielectric Films," International Electron Devices Meeting 1996, pp. 495-498 (Dec. 8-11, 1996, San Francisco, CA).
A.B. Joshi et al., "Oxynitride Gate Dielectrics for p.sup.+ -Polysilicon Gate MOS Devices," IEEE Electron Devices Letters, vol. 14, No. 12, pp. 560-562 (Dec. 1993).
H. Fang et al., "Low-Temperature Furnace-Grown Reoxidized Nitrided Oxide Gate Dielectrics as a Barrier to Boron Penetration," IEEE Electron Device Letters, vol. 13, No. 4, pp. 217-219 (Apr., 1992).
Chuan Lin et al., "Leakage Current, Reliability Characteristics, and Boron Penetration of Ultra-Thin (32-36.ANG.) O.sub.2 -Oxides and N.sub.2 O/NO Oxynitrides," International Electron Devices Meeting 1996, pp. 331-334 (Dec. 8-11, 1996--San Francisco, CA).
E. Hasegawa et al., "The Impact of Nitrogen Profile Engineering on Ultra-Thin Nitrided Oxide Films for Dual-Gate CMOS ULSI," International Electron Devices Meeting 1995, pp. 327-330 (Dec. 10-13, 1995--Washington, DC).
Hattangady et al., "Controlled Nitrogen Incorporation at the Gate Oxide Surface," Applied Physics Letters, vol. 66, No. 25, pp. 3495-3497 (Jun. 19, 1995).
Silicon Processing for the VLSI Era--vol. 1:Process Technology, by S. Wolf, published by Lattice Press, Sunset Beach, CA, 1986, pp. 182-195, 209-211, 280-283, 294, 308, 321-327. (Month Unknown).
Silicon Processing for the VLSI Era--vol. 2:Process Integration, by S. Wolf, published by Lattice Press, Sunset Beach, CA, 1990, pp. 124-131. (Month Unknown).
T. Kuroi et al., "Novel NICE (Nitrogen Implantation into CMOS Gate Electrode and Source-Drain) Structure for High Reliability and High Performance 0.25 .mu.m Dual Gate CMOS," International Electron Devices Meeting 1993, pp. 325-328 (Dec. 5-8, 1993--Washington, DC).
Silicon Processing for the VLSI Era--vol. 3: The Submicron MOSFET, by S. Wolf, published by Lattice Press, Sunset Beach, CA, 1995, pp. 496-504, 641-642, and 648-661. (Month Unknown).

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