Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1995-04-24
2001-06-19
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C257S778000, C257S781000, C257S783000
Reexamination Certificate
active
06249051
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the joining of integrated circuit elements to the next level of integration and more particularly to the formation of the bonded structure which comprises the physical and electrical connection between the integrated circuit element and the next level of integration.
(2) Description of the Related Art
In the manufacture of highly dense integrated circuits the formation of an inexpensive and highly reliable mechanical bond and electrical interconnection has long been recognized to be of key importance. Some time ago a solution to this need was patented by L. F. Miller et al in U.S. Pat. No. 3,401,126. This method worked well for many years but increasing levels of integration and circuit density have made the need for interconnections on an increasingly fine pitch of key importance.
Flip chip bonding has been done using several types of bumps. One type simply uses a lead-tin solder or indium alloy solder as the bump which bonds the integrated circuit chip to a substrate. This type of bonding can result in shorting between bumps during solder reflow. Another type of bump uses a copper ball within the lead-tin or indium alloy solder. The copper ball does not melt during solder reflow so there will not be a shorting. However since the copper ball is rigid there can be problems with cracking of joints. Another type of structure is a stack of solder bumps. This type of structure is not easily shorted during reflow and the cracking problem is not present. However, it is difficult to make fine pitch solder reflow joints with this method because of stack misalignment problems.
A method for achieving increased interconnection density was patented by K. Hatada in U.S. Pat. No. 4,749,120. This method employs a gold bump as the electrical interconnection between the integrated circuit chip and the substrate while holding the integrated circuit chip in place with a resin coating on the substrate acting as an adhesive between chip and substrate. This method has the disadvantage of a Young's Modulus for gold which is very high when compared to that of the resin. As a result of the Young's Modulus mismatch a very large bonding force is required between the integrated circuit chip and the substrate during the bump bonding process while the resin is undergoing its curing cycle. After the bonding process the gold bump will tend to return to its original shape and the recoil forces will disengage some of the bumps from the electrodes on the substrate. Another method patented by Y. Tagusa et al in U.S. Pat. No. 4,963,002 employs nickel plated plastic beads or silver particles to achieve the electrical connection but the former method suffers small contact surface area and the latter method has the further disadvantage of the relatively high Young's Modulus for silver.
U.S. Pat. No. 4,916,523 issued to Sokolovsky et al shows a unidirectional conductive adhesive to bond the integrated circuit chip to the substrate. U.S. Pat. No. 5,134,460 issued to Brady et al shows conductive metal bumps covered with a gold layer.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a solder reflow bonded structure which is not easily shorted during solder reflow, does not easily crack after solder reflow and which easily accommodates a fine pitch solder reflow. This objective is accomplished with a composite bump included in a solder joint. The composite bump includes a single polymer body with a low Young's Modulus relative to that of metals and a conductive metal coating covering the polymer body. The bonded structure includes an integrated circuit element with input/output pads, a substrate with input/output pads, composite bumps which connect the integrated circuit element input/output pads and the substrate input/output pads, and soldering metal which forms the solder joint. The bonded structure is not easily shorted during a solder reflow bonding process, can accommodate a very fine pitch solder reflow easily, and does not easily crack after solder reflow is complete. The bonded structure of this invention forms the electrical and physical connections between integrated circuit elements and the corresponding substrate wherein very dense wiring patterns can be accommodated economically and the resulting connections are extremely reliable.
It is a further object of this invention to provide a method of forming a bonded structure which includes solder joints and composite bumps. This objective is achieved by forming composite bumps on the input/output pads of an integrated circuit element or substrate, forming a layer of soldering metal on the composite bumps, bringing the integrated circuit element and substrate together and heating the solder to solder reflow temperature. Alternatively the objective can be achieved by forming composite bumps on the input/output pads of an integrated circuit element or substrate, forming a layer of soldering metal on the input/output pads which do not have the composite bumps, bringing the integrated circuit element and substrate together and heating the solder to reflow temperature.
REFERENCES:
patent: 3401126 (1968-09-01), Miller et al.
patent: 3809625 (1974-05-01), Brown et al.
patent: 4504007 (1985-03-01), Anderson, Jr. et al.
patent: 4883774 (1989-11-01), Feilchenfeld et al.
patent: 4916523 (1990-04-01), Sokolovsky et al.
patent: 4963002 (1990-10-01), Tagusa et al.
patent: 5115090 (1992-05-01), Sachdev et al.
patent: 5134460 (1992-07-01), Brady et al.
patent: 5397863 (1995-03-01), Afzali-Ardakani et al.
patent: 2-180036 (1990-07-01), None
Craig et al., “Polyimide Coatings”, Electronic Materials Handbook, vol. 1, Packaging, pp. 767-772, 1989.
Chang Shyh-Ming
Chu Chih-Chiang
Lee Yu-Chi
Ackerman Stephen B.
Chambliss Alonzo
Chaudhuri Olik
Industrial Technology Research Institute
Prescott Larry J.
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