Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1995-08-23
2002-04-02
Graybill, David E. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S615000
Reexamination Certificate
active
06365500
ABSTRACT:
RELATED PATENT APPLICATIONS
(1) Ser. No. 08/239,424, filed May 6, 1994, U.S. Pat. No. 5,393,697, entitled Composite Bump Structure and Methods of Fabrication assigned to the same assignee.
(2) Ser. No. 08/239,380, filed May 6, 1994, U.S. Pat. No. 5,731,328, entitled Composite Bump Flip Chip Bonding assigned to the same assignee.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the joining of integrated circuit elements to the next level of integration, or that level of integration to the following level, and more particularly to the formation of the bonded structure which comprises the physical and electrical connection between the integrated circuit element and the next level of integration.
(2) Description of the Related Art
In the manufacture of highly dense integrated circuits the formation of an inexpensive and highly reliable mechanical bond and electrical interconnection between the integrated circuit element and substrate has long been recognized to be of key importance. Some time ago a solution to this need was patented by L. F. Miller et al in U.S. Pat. No. 3,401,126. This method worked well for many years but increasing levels of integration and circuit density have made the need for interconnections on an increasingly fine pitch of key importance.
A method for achieving increased interconnection density was patented by K. Hatada in U.S. Pat. No. 4,749,120. This method employs a metal bump as the electrical interconnection between the integrated circuit chip and the substrate while holding the integrated circuit chip in place with a resin coating on the substrate acting as an adhesive between chip and substrate. This method has the disadvantage of a relatively high Young's Modulus for metals. As a result of the high Young's Modulus a very large bonding force is required between the integrated circuit chip and the substrate during the micro-bump bonding process while the resin is undergoing its curing cycle. After the bonding process the gold micro-bump will tend to return to its original shape and the recoil forces will disengage some of the micro-bumps from the electrodes on the substrate. Another method patented by Y. Tagusa et al in U.S. Pat. No. 4,913,002 employs nickel plated plastic beads or silver particles to achieve the electrical connection, but the former suffers from small contact surface area and the latter suffers the disadvantage of a relatively high Young's Modulus for silver.
U.S. Pat. No. 4,916,523 issued to Sokolovsky et al shows a unidirectional conductive adhesive to bond the integrated circuit chip to the substrate. U.S. Pat. No. 5,134,460 issued to Brady et al shows conductive metal bumps coated with a gold layer.
SUMMARY OF THE INVENTION
It is the principal object of the invention to provide a bonded structure comprising the electrical and physical connections between integrated circuit elements and the corresponding substrate wherein very dense wiring patterns can be accommodated economically and the resulting connections are extremely reliable.
This object is achieved with a bonded structure comprising the integrated circuit element input/output pads, composite bumps comprised of a single polymer body with a Young's Modulus which is low compared to metals and a conductive metal coating covering the polymer body, and the substrate input/output pads. The conductive metal coating covering the polymer body must be chosen to provide good adhesion to the polymer body and may include an adhesive layer and a barrier layer in addition to a conductor layer. The low Young's Modulus of the polymer, about 0.4×10
6
to 0.5×10
6
psi, allows the bond to be made with very low bonding force and greatly reduces or eliminates the force tending to separate the connections after the bonding force is removed. This results in extremely reliable physical and electrical connections between the integrated circuit element and substrate.
It is a further object of the invention to provide a method of forming a bonded structure comprising the electrical and physical connections between integrated circuit elements and the corresponding substrate wherein very dense wiring patterns can be accommodated economically and the resulting connections are extremely reliable.
This object is achieved by forming a bonded structure comprising the integrated circuit element input/output pads, composite bumps comprised of a single polymer body with a Young's Modulus which is low compared to metals and a conductive metal coating covering the polymer body, and the substrate input/output pads. The conductive metal coating covering the polymer body must be chosen to provide good adhesion to the polymer body and may include an adhesive layer and a barrier layer in addition to a conductor layer. The composite bump will be deformed during the bonding process and the low Young's Modulus of the polymer, about 0.4×10
6
to 0.5×10
6
psi, allows the bond to be made with very low bonding force and greatly reduces or eliminates the force tending to separate the connections after the bonding force is removed. The polymer body and the conductive metal coating must be chosen to be compatible with the temperatures used during the bonding process.
REFERENCES:
patent: 3401126 (1968-09-01), Miller et al.
patent: 3763550 (1973-10-01), Oakes
patent: 3809625 (1974-05-01), Brown et al.
patent: 4749120 (1988-06-01), Hatada
patent: 4865245 (1989-09-01), Schulte et al.
patent: 4916523 (1990-04-01), Sokolovsky et al.
patent: 4963002 (1990-10-01), Tagusa et al.
patent: 4965227 (1990-10-01), Cham et al.
patent: 5134460 (1992-07-01), Brady et al.
patent: 5298331 (1994-03-01), Kanakarajan et al.
patent: 5331235 (1994-07-01), Chun
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“Pressure Contact Type Chip Join Technique”;IBM TDB, W. C. Ward, vol. 18 No. 9, Feb. 1976, p. 2817.
Chang Shyh-Ming
Hu Dyi-Chung
Jou Jwo-huei
Lee Yu-Chi
Ackerman Stephen B.
Graybill David E.
Industrial Technology Research Institute
Prescott Larry J.
Saile George O.
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