Complementary transistors with controlled drain extension...

Details Complementary transistors with controlled drain extension... Complementary transistors with controlled drain extension...

2002-12-06

2004-05-04

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S303000, C438S305000, C438S595000

Reexamination Certificate

active

06730556

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to electronic circuits and are more particularly directed to electronic circuit transistors having drain extensions.
Semiconductor devices are prevalent in all aspects of electronic circuits, and the design of such devices often involves a choice from various circuit elements such as one or more different transistor devices. For example, in various applications including many high performance applications, transistors are formed with so-called drain extensions that are so named because they extend the source/drain regions of the transistor to the area under the transistor gate. Several years ago such extensions were formed in some applications using “lightly-doped drain” extensions, typically identified with the abbreviation LDD. More recently, a comparable structure has been formed, but the amount of dopant concentration in what formerly were the LDD regions has increased. As a result, these regions are more recently referred to as HDD regions due to the higher dopant concentration.
By way of further background, the following Figures and discussion illustrate one prior art approach for forming a PMOS transistor and an NMOS transistor, both including HDD regions. Looking to
FIG. 1
a
, it illustrates a cross-sectional view of an integrated circuit semiconductor device designated generally at
10
and which is built in connection with a substrate
12
. By way of example, substrate
12
is a p-type semiconductor material. Relative to substrate
12
, two areas
14
and
16
are shown in which an NMOS and PMOS transistor, respectively, are to be formed. Generally, areas
14
and
16
are isolated from one another, such as through the use of an isolating region
18
, typically formed from oxide. Looking to area
14
, a gate stack
20
is formed with a gate insulator
22
separating a gate
24
from substrate
12
. Similarly and looking to area
16
, a gate stack
40
is formed with a gate insulator
42
separating a gate
44
from an n-type well
12
′ formed within substrate
12
. After each gate stack is formed, respective sidewall spacers
25
and
45
are formed along the sidewalls of each stack
20
and
40
, respectively, such as by forming a layer of conformal oxide over the structure and then etching it to leave oxide spacers along the sidewalls of each gate stack. Once sidewall spacers
25
and
45
are formed for both transistors, at one time one transistor area is masked while a dopant implant is performed for the un-masked transistor and, thereafter, the masking process is reversed and the implant is performed for the other transistor. For example, assume in a first instance that area
16
is masked, and then an n-type dopant, such as arsenic, is implanted in area
14
. This n-type implant forms HDD regions
26
that self-align with respect to sidewall spacers
25
. Next, in a second instance, area
14
is masked, and then a p-type dopant is implanted in area
16
. In the prior art, one common p-type dopant has been boron, and more recently favor has been found in the use of BF
2
rather than boron alone. This p-type implant forms HDD
46
regions that self-align with respect to sidewall spacers
45
.
FIG. 1
b
illustrates device
10
after additional processing. Specifically, after the steps shown in
FIG. 1
a
, an anneal is performed. The annealing step activates the dopants in HDD regions
26
and
46
. In response to the anneal, the dopants in HDD regions
26
and
46
tend to migrate laterally, that is, the dopant profile in each of regions
26
and
46
causes a migration in response to the anneal. As a result, in
FIG. 1
b
note that regions
26
and
46
are now labeled
26
′ and
46
′ to distinguish them from
FIG. 1
a
, where the distinction is helpful because it represents that each HDD region has encroached laterally under its respective gate stack.
FIG. 1
c
illustrates device
10
after additional processing. Specifically, after the steps shown in
FIG. 1
b
, additional respective sidewall spacers
28
and
48
are formed along the sidewall spacers
25
and
45
of each transistor, respectively. Spacers
28
and
48
also may be formed by forming a layer of conformal oxide over the structure and then etching it to leave oxide spacers along the previously-formed sidewalls of each gate stack. Once sidewall spacers
28
and
48
are formed for both gate stacks
20
and
40
, at one time one transistor area is masked while a dopant implant is performed for the un-masked transistor and, thereafter, the mask process is reversed and the implant is performed for the other transistor. For example, assume in a first instance that area
16
is masked, and then an n-type dopant (e.g., arsenic) is implanted in area
14
. This n-type implant forms deep source/drain regions
30
that self-align with respect to sidewall spacers
28
. Next, in a second instance, area
14
is masked, and thereafter a p type dopant (e.g., BF2) is implanted in area
16
. This p-type implant forms deep source/drain regions
50
that self align with respect to sidewall spacers
48
.
FIG. 1
d
illustrates device
10
after additional processing. Specifically, after the steps shown in
FIG. 1
c
, an additional anneal is performed. The annealing step activates the dopants in deep source/drain regions
30
and
50
. In response to the anneal, the dopant profiles of source/drain regions
30
and
50
are such that source/drain regions
30
and
50
migrate laterally and they also further combine with HDD regions
26
′ and
46
′, respectively. As a result, in
FIG. 1
d
the combined regions are shown for the NMOS transistor and the PMOS transistor as
32
and
52
, respectively. Lastly, following the preceding steps, various other steps may be taken to form other aspects with respect to the PMOS and NMOS transistors, including other layers for connectivity and the like.
While device
10
has performed adequately in many circuits and applications, it has been observed in connection with the present embodiments that device
10
may provide drawbacks. Specifically, in many device fabrication processes it is desirable to have certain comparable aspects for both PMOS and NMOS devices. In the case of device
10
, one such instance of this principle arises with respect to what is referred to as the “overlap” between each HDD region and the adjacent sidewall of its corresponding gate
24
or
44
. Returning briefly to
FIG. 1
d
, such an overlap is shown for each transistor, with the NMOS transistor having an overlap OV
1
N
and the PMOS transistor having an overlap OV
1
P
. Returning to the above-introduced principle of comparable transistor aspects, it is therefore desirable that the length of overlap OV
1
N
and overlap OV
1
P
are the same or very similar. This is desirable, for example, because the amount of overlap may affect the operational characteristics of each device, where typically it is desirable that the PMOS and NMOS transistors have certain characteristics (in complementary fashion) that are the same or very similar.
Given the above, the present inventors recognize that the process of
FIGS. 1
a
through
1
d
does not necessarily provide equal values for overlaps OV
1
N
and OV
1
P
. Specifically, it is observed that the arsenic, used for the n-type implant, diffuses in response to an anneal at a slower rate than the BF
2
, used for the p-type implant. As a result, if the same dosage and energies are used for both the arsenic and BF
2
implants, then overlaps OV
1
N
and OV
1
P
, caused by the anneal, are unequal. To compensate for this variance, one approach in the prior art has been to lower the dose (or energy) used in the BF
2
implant that forms HDD regions
46
in the PMOS transistor as compared to the dose (or energy) used in the arsenic implant that forms HDD regions
26
in the NMOS transistor. Still further, however, this alternative is also observed to provide a drawback. Specifically, by lowering the dose and/or

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