Complementary MISFET

Details Complementary MISFET Complementary MISFET

2001-09-25

2004-05-18

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S299000

Reexamination Certificate

active

06737309

ABSTRACT:

CROSS-REFERECCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-293929, filed Sep. 27, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an improvement of gate electrodes of an n-type MIS transistor and a p-type MIS transistor.
2. Description of the Related Art
Miniaturization of devices is indispensable in enhancing the performance of MIS transistors. However, a silicon oxide film, which is currently used as a gate insulation film, has a low dielectric constant, and thus the capacitance of the gate insulation film cannot be increased. In addition, since a polysilicon used as a gate electrode has a high resistivity, it is difficult to decrease the resistance of the gate electrode. To solve these problems, there is an idea that a high dielectric constant material is used for the gate insulation film and a metallic material is used for the gate electrode.
However, these materials have drawbacks in that the heat resistance thereof is lower than that of currently used materials. A damascene gate technique has been proposed as a technique wherein a gate insulation film and a gate electrode can be formed after a high-temperature process is carried out.
In a case where a metal is buried as gate electrodes by the damascene gate technique, the gate electrodes of an n-type MISFET and a p-type MISFET are formed of a single metal and the work function of the gate electrodes is fixed. Thus, unlike the case of polysilicon gates, it is not possible to optimize threshold values by forming different gate electrodes in n-type and p-type devices. A dual metal gate process is thus required in order to form gate electrodes of different materials in n-type and p-type devices.
The inventors previously filed a patent application (application Ser. No. 09/559,356) for a technique for forming different metal gate electrodes in n-type and p-type devices. The steps of a process of fabricating a semiconductor device according to the method of this application will now be described with reference to
FIGS. 3A
to
3
J.
To start with, a device isolation region
101
is formed on a silicon substrate
100
by means of an STI (shallow trench isolation) technique, etc. An p-well
102
is formed in a formation region of an n-type MISFET and a n-well
103
is formed in a formation region of a n-type MISFET. A dummy gate lamination structure is then formed as a dummy gate that is to be removed later, by means of techniques of oxidation, CVD, lithography, RIE, etc. The dummy gate lamination structure comprises a gate oxide film
104
, which is, e.g. about 6 nm thick, a polysilicon
105
, which is about 150 nm thick, and a silicon nitride film
106
, which is about 50 nm thick. An extension diffusion layer region
107
is formed using an ion implantation technique. A gate side wall
108
with a thickness of about 40 nm, which is formed of a silicon nitride film, is formed by CVD and RIE techniques.
In
FIG. 3B
, a source/drain diffusion layer
109
is formed by an ion implantation technique. Then, using the dummy gate as a mask, a silicide
110
of cobalt, titanium, etc. with a thickness of about 40 nm is formed only in the source/drain region by means of a salicide process technique.
In
FIG. 3C
, a silicon oxide film, for example, is deposited by CVD as an interlayer film
111
. The silicon oxide film is then flattened by CMP to expose surfaces of the silicon nitride film
106
and gate side wall
108
at an upper part of the dummy gate.
In
FIG. 3D
, the silicon nitride film
106
at the upper part of the dummy gate is selectively removed relative to the interlayer film
111
by using a phosphoric acid, for instance. At this time, the gate side wall
108
at the side wall of the gate is also etched away to a level equal to the level of the polysilicon
105
. Subsequently, the polysilicon of the dummy gate is selectively removed relative to the interlayer film
111
and the gate side wall
108
of the silicon nitride film by means of, e.g. a radial atom etching technique. Thus, a gate trench
112
is created. The dummy gate oxide film
104
is provided at the bottom of the gate trench
112
.
In
FIG. 3E
, the dummy gate oxide film
104
is removed by a wet process using hydrofluoric acid, etc., thereby exposing the p-well
102
or n-well
103
at the bottom of the gate trench
112
.
A gate insulation film
113
of, e.g. a hafnium oxide film is formed as a high dielectric constant insulator over the entire surface of the resultant structure.
In
FIG. 3F
, a hafnium nitride film
114
, as an example of metal having a work function of 4.6 eV or less, is formed by CVD or sputtering with a thickness of about 10 nm, or preferably less than 10 nm, on the entire surface of the resultant.
The steps of
FIGS. 3A
to
3
F are carried out for both the n-type MIS transistor formation region and p-type MIS transistor formation region, but these Figures show only one of these regions. As regards the subsequent steps,
FIGS. 3G
to
3
J show both of the n-type MIS transistor (n-type MISFET) and p-type MIS transistor (p-type MISFET).
In
FIG. 3G
, that portion of a resist
115
, which lies in the p-type MISFET region, is removed by lithography.
In
FIG. 3H
, wet etching is performed using hydrogen peroxide solution, thereby removing the hafnium nitride film
114
from the p-type region alone. At this time, the gate insulation film
113
, which is the hafnium oxide film, is not etched since it is insoluble in the hydrogen peroxide solution.
In
FIG. 3I
, the resist
115
is removed, and tantalum nitride
116
, as an example of a material having a work function of 4.6 eV or more, is deposited with a thickness of at least about 10 nm.
In
FIG. 3J
, aluminum
117
is deposited as a low-resistance gate electrode material on the entire surface of the resultant by means of sputtering or CVD. Then, the aluminum is subjected to CMP, thus burying the aluminum
117
in the gate trenches.
A CMISFET is fabricated through the above-described steps, which has gate electrode structures comprising, respectively, an n-type lamination structure of the hafnium nitride film
114
, tantalum nitride
116
and aluminum
117
, and a p-type lamination structure of the tantalum nitride film
116
and aluminum
117
. Accordingly, the threshold values can be optimized since the work function of the gate electrode of the n-type device is 4.6 eV or less and the work function of the gate electrode of the p-type device is 4.6 eV or more.
This structure has a problem, however.
FIGS. 4A and 4B
are enlarged views of the gate electrode portions of the n-type MISFET and p-type MISFET. In the n-type MISFET, a width L
A1
of the aluminum of the gate electrode is expressed by
L
A1
=L
G
−2×
L
TaN
−2×
L
HfN
where L
A1
is a width of the aluminum
117
, L
G
is a gate length, L
TaN
is a width of the tantalum nitride film
116
, and L
HfN
is a width of the hafnium nitride film
114
.
The tantalum nitride film
116
functions to control the work function of the gate electrode, and also serves as a barrier metal for preventing the upper electrode, i.e. the aluminum
117
, from diffusing in the gate insulation film. Accordingly, in view of the gate breakdown voltage and reliability, it is necessary that the thickness of the tantalum nitride film
116
be at least about 10 nm or more.
However, in the case where the gate length (L
G
) is 40 nm or less, if the film thickness (L
TaN
) of the tantalum nitride film
116
is 10 nm and the thickness (L
HfN
) of the hafnium nitride film
114
is 10 nm, the width (L
A1
) of the aluminum
117
would be 0 nm. Thus, if the gate length (L
G
) is 40 nm or less, it is impossible to bury the aluminum
117
. As a result, the gate resistance greatly increases and a high-performance CMISFET cannot be fabricated. The thickness o

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