Complementary metal-oxide semiconductor device having source/dra

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438232, 438306, 438307, H01L 218238

Patent

active

060749067

ABSTRACT:
A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively. A third n-type dopant is selectively implanted into the NMOS active region using the second NMOS spacer as a mask to form a third n-doped region deeper than the second n-doped region in the NMOS active region. A second p-type dopant is selectively implanted into the PMOS active region using the second PMOS spacer as a mask to form a second p-doped region in the PMOS active region deeper than the first p-doped region.

REFERENCES:
patent: 5650341 (1997-07-01), Yang et al.
patent: 5827747 (1998-10-01), Wang et al.
patent: 5849616 (1998-12-01), Ogoh
S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, vol. 1, Lattice Press, p. 408, 1986.
Wolf, S., Silicon Processing for the VLSI Era, vol. 2--Process Integration, Lattice Press, Sunset Beach, CA 90742 (1990); pp. 354-363 (ISBN 0-961672-4-5).

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