Compensated input receiver with controlled switch-point

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

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Details

326 30, 326 34, 326 87, H03K 1716, H03K 19003

Patent

active

060844264

ABSTRACT:
A compensated CMOS receiver includes an inverter, at least one compensation transistor coupled between a first voltage and the output of the inverter, a comparison circuit coupled to the output of the inverter, and a control circuit coupled to the comparison circuit and the compensation transistor. When the receiver is driven to a calibration state, the comparison circuit generates an output signal that reflects the difference between the inverter's output voltage and a switch-point reference. The control circuit adjusts the one or more compensation transistors according to the difference signal generated by the comparison circuit.

REFERENCES:
patent: 5117124 (1992-05-01), Dickie
patent: 5134311 (1992-07-01), Biber et al.
patent: 5214319 (1993-05-01), Abdi
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5373400 (1994-12-01), Kovacs
patent: 5465059 (1995-11-01), Pan et al.
patent: 5576842 (1996-11-01), Choi

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