Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
1998-06-29
2001-01-09
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C326S040000
Reexamination Certificate
active
06172900
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to Random Access Memory (RAM) cells. More particularly, this invention relates to a compact, low voltage, noise-immune RAM cell for use in programmable logic devices and other electronic components.
BACKGROUND OF THE INVENTION
Random Access Memory (RAM) cells are well known in the art. Many RAM cells are optimized for frequent programming and rapid access times. The present invention is directed toward applications where these conditions are not critical. For example, in many programmable logic devices, RAM cell access times are not critical and the RAM cells are not programmed frequently.
FIG. 1
illustrates three prior art RAM cells
20
A,
20
B, and
20
C in a First-In-First-Out (FIFO) configuration. Each RAM cell
20
includes a forward inverter
22
and a feedback inverter
24
collectively operating to store a single binary digit (bit). An address line (ADD) is associated with each RAM cell
20
. Each address line is used to control an access transistor T.
The circuit of
FIG. 1
operates in a FIFO manner because each RAM cell is driven by the RAM cell before it. For example, during programming, the address line (ADD
—
1) for RAM cell
20
B is driven high, turning-on access transistor T
1
. As a result, the bit stored in RAM cell
20
A is written into RAM cell
20
B. This process is repeated until the bit is written to the desired RAM cell of the series string of RAM cells.
There are a number of problems with a FIFO RAM cell of the type shown in FIG.
1
. One drawback is that it requires a relatively high supply voltage. That is, to successfully write a logical zero onto an output node of a destination cell, a logical one needs to be written into the destination cell from a source cell. For example, to obtain a logical zero at the output of destination cell
20
C, a logical one must be written to the input of the cell. To insure a sufficient trip voltage for the inverter
22
C, a relatively large voltage must be generated by the source cell
20
B to overcome the voltage drop associated with the access transistor T
2
at the input of the destination cell
20
C.
Another problem with the prior art device of
FIG. 1
is that it is relatively space intensive. The feedback inverter
24
of each cell
20
is a weak device with a relatively large channel length. The access transistors T are relatively conductive devices with relatively larger widths. These geometries require a relatively large amount of die area.
Another problem associated with the prior art device of
FIG. 1
is its susceptibility to noise. A noise glitch on an address line (ADD) may turn on an access transistor T, resulting in a cell being overwritten by a previous serial cell. For example, a noise glitch on address line ADD
—
1 may turn on access transistor T
1
, causing a logical one from cell
20
A to be written over a logical zero at the input of cell
20
B.
In view of the foregoing, it would be highly desirable to develop a RAM cell that is noise-immune, compact, and does not require a large supply voltage.
SUMMARY OF THE INVENTION
A random access memory cell includes a forward inverter and a feedback inverter connected to the forward inverter. The feedback inverter includes a ground access transistor configured to selectively connect and isolate the feedback inverter to ground. The ground access transistor is isolated from ground in response to a first digital state global clear signal generated during a global clear state. A set of random access memory cells are simultaneously programmed to store identical values in response to the first digital state global clear signal during the global clear state. The ground access transistor is connected to ground in response to a second digital state global clear signal generated during a programming state. Selected random access memory cells are programmed to store selected values in response to the second digital state global clear signal during the programming state. The circuit allows for a compact, low voltage, noise-immune random access memory cell optimized for field programmable logic devices and other applications where write access times and programming times are not critical.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1
illustrates a set of RAM cells constructed in accordance with the prior art.
FIG. 2
illustrates a set of RAM cells constructed in accordance with an embodiment of the invention.
FIG. 3
illustrates the operation of a RAM cell of
FIG. 2
during a global clear operation.
FIG. 4
illustrates the operation of a RAM cell of
FIG. 2
when programming a logical one value.
FIG. 5
illustrates the operation of a RAM cell of
FIG. 2
when programming a logical zero value.
FIG. 6
illustrates an alternate embodiment of a feedback inverter that may be used in accordance with the invention.
FIG. 7
illustrates a field programmable logic device incorporating the RAM cell of the invention, the field programmable logic device forming a portion of a data processing system.
REFERENCES:
patent: 5828608 (1998-10-01), Nguyen et al.
patent: 5831907 (1998-11-01), Trimberger
U.S. application No. 09/038,123, filed Mar. 11, 1998, pending.
Altera Corporation
Galliani William S.
Nguyen Tan T.
Pennie & Edmonds LLP
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