Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-06-22
2001-06-05
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185230, C365S185260
Reexamination Certificate
active
06243296
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuit memory technology. More specifically, the present invention provides a compact nonvolatile memory cell in which a write control line is directly coupled to a tunnel diode of the memory cells, and techniques of operating, programming, and erasing such a memory cell to enhance the reliability and service life of the memory cell.
Memory cells are used in the implementation of many types of electronic devices and integrated circuits. These devices include microprocessors, static random access memories (SRAMs), erasable-programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), Flash EEPROM memories, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), and application specific integrated circuits (ASICs), among others. Memory cells are used to store the data and other information for these and other integrated circuits.
As integrated circuit technology and semiconductor processing continue to advance, there is a need for greater densities and functionality in integrated circuits, which are often determined in a large part by the size of the memory cells. Therefore, it is desirable to achieve memory cells with smaller cell sizes. Further, it is desirable that the memory cells have improved operating characteristics, such as lower power consumption, nonvolatility, greater device longevity, improved data retention, better transient performance, superior voltage and current attributes, and improvements in other similar attributes.
There is further a need to provide techniques for programming and erasing the memory cells reliably. For example, during the program operation, unselected memory cells which are not to be configured should be left undisturbed. There is further a need for improved techniques of evaluating the physical characteristics of nonvolatile memory cells. These physical characteristics or properties are important in the determination of an integrated circuit's service life and reliability. These measurements are also useful for study and use in improving memory cells.
As can be seen, improved memory cells and techniques for operating, programming, and erasing these cells are needed. Improved techniques are also needed for increasing the reliability and longevity of these memory devices.
SUMMARY OF THE INVENTION
The present invention provides a compact nonvolatile memory cell to store logical data. The memory cell may be used to form arrays of memory cells. A write control line for the memory cell is directly coupled to a tunnel diode of the memory cell. During programming of a selected memory cell, unselected memory cells are not disturbed, and oxide stress for the unselected memory cells is minimized. The present invention also provides techniques for operating, programming, and erasing the memory cell. During the configuration of a selected memory cell, half-select voltages may be used on a control gate line and write control line of the memory cell to prevent disturb of unselected memory cells.
Specifically, the memory cell of the present invention includes: a first transistor coupled between a DL line and an internal node, wherein a control electrode of the first transistor is coupled to an RL line; a second transistor coupled between the internal node and an SL line, where the second transistor includes a floating gate coupled to a CG line; and a write control line coupled directly to a tunnel diode of the memory cell. For the memory cell, the write control line is connected to the tunnel diode without passing through a transistor device. The memory cell further includes a tunnel dielectric, where charge is transferred between the tunnel diode and the floating gate through the tunnel dielectric.
Furthermore, half-select voltages are coupled to unaccessed CG and WC lines in an array of memory cells to avoid disturbing a state of unaccessed cells. In particular, a technique of the present invention includes: providing voltage to control lines of a selected memory cell to place the selected memory cell in a desired configured state; and providing a first half-select voltage to a first control line of an unselected memory cell, where the first half-select voltage is an intermediate voltage between ground and a V
PP
voltage. Further, a second half-select voltage may be provided to a second control line of the unselected memory cell. The first and second half-select voltages may be different. Furthermore, in an embodiment of the layout of the memory cell of the present invention, the first and second control line are transverse.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
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Altera Corporation
Dinh Son T.
Townsend and Townsend / and Crew LLP
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