Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-03-06
2007-03-06
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S003000
Reexamination Certificate
active
10660243
ABSTRACT:
Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.
REFERENCES:
patent: 5414713 (1995-05-01), Waschura et al.
patent: 6618686 (2003-09-01), Allamsetty
patent: 6647301 (2003-11-01), Sederlund et al.
patent: 2005/0021749 (2005-01-01), Donlin et al.
Black William C.
Das Bodhisattva
Irwin Scott A.
Shafer Matthew S.
Chung Phung My
Webostad W. Eric
Xilinx , Inc.
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