Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-01-31
2008-08-12
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07412633
ABSTRACT:
An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals.
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Ashfield Edmond John Simon
Field Ian
Houlihane Thomas Sean
Kimelman Paul
ARM Limited
Kerveros James C
Nixon & Vanderhye P.C.
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