Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-23
2003-07-08
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06591387
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a communication system for controlling terminal units through boundary scan elements, and particularly to a communication system which can quickly transmit output data from the terminal units.
BACKGROUND OF THE INVENTION
A boundary scan test method has been proposed as one of the inspection methods with a plurality of IC chips arranged over a printed wire board with printed wiring formed thereon, to see whether or not connection between each IC chip and each printed wiring is properly made and whether or not each printed wiring is not broken.
This boundary scan test method can be applied to integrated circuits (IC chips) into which boundary scan elements are incorporated. The boundary scan element, for example as shown in
FIG. 4
, includes a plurality of boundary cells
114
individually provided between input/output terminals of an internal logic
111
for implementing the inherent functions of the integrated circuit
110
and input/output terminals
112
/
113
of the integrated circuit
110
, a TAP controller (TAP circuit)
119
for controlling input and output of data to or from the boundary cells
114
, a TDI terminal
120
for receiving test data, a TDO terminal
121
for transmitting test data, a TCK terminal
122
into which a clock signal is input, and a TMS terminal
123
for receiving a mode signal for switching the operation mode of the TAP controller
119
; and, if required, it is further provided with a bypass register
115
, an ID CODE register
116
, an instruction register
117
, a TRS terminal
124
for receiving a reset signal, or the like. In this connection, the bypass register
115
to instruction register
117
is referred to as boundary scan register (
118
).
To describe the respective terminals or the signals to be input/output through the respective terminals in detail, TDI (Test Data In) is a signal for serial-inputting instructions and data to a test logic, and is sampled at rising edges of TCK. TDO (Test Data Out) is a signal for serial-outputting data from the test logic, the output value being changed at falling edges of TCK. TCK (Test Clock) supplies a clock to the test logic. It is a dedicated input for enabling the use of a serial test data path independent of the system clock inherent to the component. TMS (Test Mode Select) is a signal for controlling the test operation, and is sampled at rising edges of TCK. The TAP controller decodes this signal. TRST (Test Reset) is a negative logic symbol for a synchronously initializing the TAP controller, and is optional.
The integrated circuit
110
into which such boundary scan element is incorporated can be tested on the operating state thereof and the connecting relationship between this integrated circuit
110
and external devices, by the procedures described below.
First, in checking the quality of the internal logic
111
of the integrated circuit
110
, serial data (test data) are input to the TDI terminal
120
of the integrated circuit
110
as they are shifted, and thereby the test data are set into the respective boundary cells
114
corresponding to the respective input terminals
112
. In this state, the integrated circuit
110
is operated before the data set in the respective boundary cells
114
corresponding to the respective output terminals
113
are shifted for output from the TDO terminal
121
, and, on the basis of the corresponding relationship between the serial data (test result data) thus obtained and the test data input to this integrated circuit
110
, the internal logic
111
of the integrated circuit
110
is tested for its quality.
The boundary scan test method can also be carried out on a plurality of integrated circuits as long as the boundary scan elements are incorporated therein.
For example, a plurality of integrated circuits
110
mounted on a substrate
126
as shown in
FIG. 5
can also be subjected to a test for breakage and the like of the printed patterns between the integrated circuits
110
, along with a test on the integrated circuits
110
themselves.
In this case, the respective boundary scan elements incorporated in the plurality of integrated circuits
110
are connected in series with each other. Specifically, the TDO terminal
121
of the first integrated circuit
110
(the left in the drawing) and the TDI terminal
120
of the second integrated circuit
110
(the right in the drawing) are connected with each other, the output terminal
129
of a boundary scan controller board
128
provided in host computer unit
127
or the like and the TDI terminal
120
of the first integrated circuit
110
are connected with each other, and the input terminal
130
of the boundary scan controller board
128
and the TDO terminal
121
of the second integrated circuit
110
are connected with each other. The test procedures are as follows:
In testing breakage, short circuit, and the like of the printed patterns, a test data preparing tool
131
or the like is used to prepare test data (serial data), which is output from the output terminal
129
of the boundary scan controller board
128
and is input to the TDI terminal
120
of the first integrated circuit
110
while shifted, setting the test data into the respective boundary cells
114
corresponding to the respective output terminals
113
in this integrated circuit
110
. In this state, the data stored in these respective boundary cells
114
are output from the respective output terminals
113
provided in the first integrated circuit
110
as shown in
FIG. 6
, and are input through the respective printed patterns
133
constituting a system bus and the like to the respective input terminals
112
of the second integrated circuit
110
, and further fetched into the respective boundary cells
114
corresponding to these respective input terminals
112
.
Thereafter, the data stored in the respective boundary cells
114
of these respective integrated circuits
110
are shifted and fetched through the input terminal
130
of the boundary scan controller board
128
as they are analyzed by using a test result analyzing tool
132
or the like, so that a test can be made for breakage, short circuit, and the like in such a test range
135
as the printed patterns
133
providing connection between the integrated circuits
110
.
Next, in inspecting the internal logic
111
of the respective integrated circuits
110
, test data are output from the output terminal
129
of the boundary scan controller board
128
, and are input to the TDI terminal
120
of the first integrated circuit
110
as they are shifted, so as to be set into the respective boundary cells
114
corresponding to the respective input terminals
112
of this integrated circuit
110
as shown in FIG.
8
.
Subsequently, this integrated circuit
110
is operated, and the resulting data are fetched into the respective boundary cells
114
corresponding to the respective output terminals
113
before the data stored in these respective boundary cells
114
are shifted to be output from the TDO terminal
121
of the first integrated circuit
110
. Here, the second integrated circuit
110
is brought into a bypass state as shown in
FIG. 7
by the boundary scan controller board
128
, so that the data output from the TDO terminal
121
are bypassed through the second integrated circuit
110
and fetched through the input terminal
130
of the boundary scan controller board
128
. Then, the test analyzing tool
132
or the like can be used for analysis of the fetched data to test whether or not the first integrated circuit
110
operates properly.
Next, in the cases of inspecting the second integrated circuit
110
, the boundary scan controller board
128
similarly brings the first integrated circuit
110
into a bypass state as shown in
FIG. 7
before test data are output from the output terminal
129
of the boundary scan controller board
128
and bypassed through the first integrated circuit
110
. Then, the test data are input to the TDI terminal
120
of the second integrated circuit
110
while
Abraham Esaw
De'cady Albert
Duaxes Corporation
Kanesaka & Takeuchi
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