Combined system responses in a chip multiprocessor

Details Combined system responses in a chip multiprocessor Combined system responses in a chip multiprocessor

2007-11-13

2007-11-13

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: support

Computer power control

By external command

C711S141000, C711S144000, C713S320000

Reexamination Certificate

active

10956537

ABSTRACT:
In one embodiment, a node comprises, integrated onto a single integrated circuit chip (in some embodiments), a plurality of processor cores and a node controller coupled to the plurality of processor cores. The node controller is coupled to receive an external request transmitted to the node, and is configured to transmit a corresponding request to at least a subset of the plurality of processor cores responsive to the external request. The node controller is configured to receive respective responses from each processor core of the subset. Each processor core transmits the respective response independently in response to servicing the corresponding request and is capable of transmitting the response on different clock cycles than other processor cores. The node controller is configured to transmit an external response to the external request responsive to receiving each of the respective responses.

REFERENCES:
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patent: 6665788 (2003-12-01), Hughes
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patent: 7069392 (2006-06-01), Kota et al.
patent: 7174467 (2007-02-01), Helms et al.
patent: 2003/0217233 (2003-11-01), Rowlands et al.

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