Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-11-20
2007-11-20
Lebentritt, Michael (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S058000, C438S143000, C438S310000, C438S402000, C438S417000, C438S622000, C438S623000, C438S624000, C438S625000, C438S656000, C438S672000, C438S675000, C438S683000, C438S685000, C438S687000, C257S758000, C257S759000, C257S760000, C257S761000
Reexamination Certificate
active
11027435
ABSTRACT:
A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a predetermined device is formed; depositing a thin Hf layer on the substrate; performing a thermal treatment of the substrate to getter oxygen and forming a barrier layer; and filling copper into the via hole and the trench.
REFERENCES:
patent: 5953615 (1999-09-01), Yu
patent: 6015747 (2000-01-01), Lopatin et al.
patent: 6069068 (2000-05-01), Rathore et al.
patent: 6130161 (2000-10-01), Ashley et al.
patent: 6180523 (2001-01-01), Lee et al.
patent: 6194279 (2001-02-01), Chen et al.
patent: 6235633 (2001-05-01), Jang
patent: 6258710 (2001-07-01), Rathore et al.
patent: 6287954 (2001-09-01), Ashley et al.
patent: 6331485 (2001-12-01), Miyamoto
patent: 6348731 (2002-02-01), Ashley et al.
patent: 6461914 (2002-10-01), Roberts et al.
patent: 6476454 (2002-11-01), Suguro
patent: 6583021 (2003-06-01), Song
patent: 6607958 (2003-08-01), Suguro
patent: 6750541 (2004-06-01), Ohtsuka et al.
patent: 6764899 (2004-07-01), Yoon
patent: 6838352 (2005-01-01), Zhao
patent: 6849927 (2005-02-01), Farrar
patent: 6869871 (2005-03-01), Choi
patent: 6949461 (2005-09-01), Malhotra et al.
patent: 6992005 (2006-01-01), Ohtsuka et al.
patent: 2001/0025999 (2001-10-01), Suguro
patent: 2002/0006725 (2002-01-01), Farrar
patent: 2002/0048931 (2002-04-01), Farrar
patent: 2002/0158338 (2002-10-01), Ohtsuka et al.
patent: 2002/0197844 (2002-12-01), Johnson et al.
patent: 2003/0011043 (2003-01-01), Roberts
patent: 2003/0027393 (2003-02-01), Suguro
patent: 2003/0096467 (2003-05-01), Park et al.
patent: 2004/0087135 (2004-05-01), Canaperi et al.
patent: 2004/0188839 (2004-09-01), Ohtsuka et al.
patent: 4-127454 (1992-04-01), None
patent: 2001-274380 (2001-10-01), None
patent: 2002-367994 (2002-12-01), None
patent: WO 02/067319 (2002-08-01), None
Jung Joo Kim; Method of Fabricating Semiconductor Device; U.S. Appl. No. 11/027,839, filed Dec. 29, 2004; 18 Pages and 2 Drawing Sheets; Assignee; Donghu Anam Semiconductor Inc.
Jung Joo Kim: Method of Fabricating Semiconductor Device; U.S. Appl. No. 11/027,851, filed Dec. 29, 2004; 15 Pages and 2 Drawing Sheets; Assignee; Donghu Anam Semiconductor Inc.
Yoshihiko Toyoda and Takeshi Mori; Semiconductor Device; Patent Abstracts of Japan: Publication No. 2002-367994; Publication Date: Dec. 20, 2002.
Kyoichi Suguro; Semiconductor Device and Manufacturing Method Thereof; Patent Abstracts of Japan; Publication No. 2001-274380; Publication Date: Oct. 5, 2001.
Takuya Kato; Semiconductor Device; Patent Abstracts of Japan; Publication No. 04-127454; Publication Date: Apr. 28, 1992.
Dongbu Electronics Co. Ltd.
Fortney Andrew D.
Lebentritt Michael
Mitchell James M
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