Combined receiver and latch

Details Combined receiver and latch Combined receiver and latch

2006-09-05

2006-09-05

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S203000, C365S230080

Reexamination Certificate

active

07102933

ABSTRACT:
A combined receiver and latch circuit is configured to receive an external clock signal, an external reference voltage and an external command signal. The circuit includes first and second nodes, first and second control gates, and an output circuit. The first and second nodes are each configured to be precharged under the control of the clock signal. The first control gate is configured to receive the reference voltage. The second control gate configured to receive the command signal. The output circuit is coupled to the first and second nodes. The first and second nodes are alternatively discharged by the first and second control gates in response to the reference voltage and the command signal. The output circuit is configured to be latched upon the alternative discharge of the first and second node.

REFERENCES:
patent: 5825713 (1998-10-01), Lee
patent: 6490224 (2002-12-01), Manning
patent: 6510095 (2003-01-01), Matsuzaki et al.
patent: 6522172 (2003-02-01), Keeth et al.
patent: 6738295 (2004-05-01), Kim
patent: 6757214 (2004-06-01), Kawaguchi et al.
patent: 6909658 (2005-06-01), Arimoto et al.

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