Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1998-09-03
2002-08-20
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S471000, C438S477000, C438S787000
Reexamination Certificate
active
06436846
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is directed to a combined preanneal/oxidation step using rapid thermal processing (RTP) in DRAM technologies for preannealing silicon wafers. In particular, in an improved process for preannealing silicon wafers, the invention method simultaneously forms a denuded zone (DZ) and a pad oxide of a given thickness by a single RTP process.
2. Description of the Prior Art
In the process of preparing silicon wafers, oxygen is present in Si ingots after Czochralski growth. The origin of the oxygen is the quartz crucible which contains the Si melt during growth and which partly dissolves in it.
When the wafers are cut from the ingot, this oxygen is still contained in the wafers, mostly in interstitial form. Therefore, the first step in DRAM technologies is to anneal the wafers in a complicated high temperature process. In this complicated high temperature process, the objective or target is to outdiffuse the oxygen from a 10-20 &mgr;m thick layer of the wafer surface and at the same time to form SiO
2
precipitates in the wafer bulk. This preanneal step creates the “denuded zone” (DZ) or region devoid of oxygen-related defects near the surface of wafer required for processing, and it provides wafers with a high internal gettering capability. During preanneal, a thin oxide layer is usually grown. However, the disadvantage of this formed oxide is that it has an uncontrolled thickness and it must be stripped prior to the formation of the pad oxide.
In a method for preparing silicon wafers, an intrinsic-gettering process is disclosed in U.S. Pat. No. 5,674,756. The process comprises heating a silicon wafer containing oxygen precipitate nuclei from room temperature up to 800° to about 1000° C. at a rate of at least 10° C./minute and holding the wafer at this temperature for 0.5 to 20 minutes to obtain a silicon wafer with effective intrinsic gettering. In this process, it is indicated that when the holding time exceeds 20 minutes, a DZ layer with an excessive thickness is obtained and oxygen precipitate nuclei are grown into stable sizes during the holding time.
U.S. Pat. No. 4,597,804 discloses a method of forming a denuded wafer by intrinsic gettering comprising annealing the silicon wafer at an annealing temperature selected from a range of 500° through 1300° C. by heating the silicon wafer such that the annealing temperature corresponds to a first temperature selected from a range of 500° C. through 900° C., and increasing the annealing temperature to a second temperature selected from a range of 950° C. through 1300° C., the annealing temperature being increased from a first temperature to the second temperature at a rate not exceeding 14° C./minute.
A process for producing a semi-conductor silicon wafer is disclosed in U.S. Pat. No. 5,534,294, and comprises: forming an oxide film with a thickness of 1 nm to 3 nm on one side of a silicon wafer; depositing a polycrystal silicon on the oxide film formed; and subjecting the silicon wafer to a heat treatment in an inert gas, a reducing gas or a mixture thereof in a manner where the other side of the silicon wafer is exposed to the gases, so that oxygen is discharged from the other side whereby a denuded zone is formed on the other side. It is indicated that the silicon wafer obtained as a result of this process has a surface denuded zone formed on the top side.
U.S. Pat. No. 5,401,669 discloses a process for preparation of silicon wafers having controlled distribution of the density of the oxygen precipitate nucleation centers. The process is accomplished by exposing an unshielded face of the wafer to an atmosphere which contains nitrogen or a nitrogen compound gas during a rapid thermal treatment at a temperature of at least 1175° C., while shielding the other face of the wafer from the atmosphere during the rapid thermal treatment to generate nucleation centers which serve as sites for the growth of oxygen precipitates during a subsequent heat treatment, the nucleation centers having a peak density proximate the unshielded face of the wafer.
There is a need in the art of preparing silicon wafers for simultaneously forming an oxide of a given target thickness and a denuded zone.
There is a further need in the art of preparing silicon wafers to eliminate the disadvantage that an oxide of uncontrolled thickness formed by the preanneal process must be stripped prior to the formation of the pad oxide.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a process for making silicon wafers by simultaneously forming an oxide of a given target thickness and a denuded zone.
Another object of the present invention is to provide a process for forming silicon wafers by providing an oxide of controlled thickness formed by a preanneal step that does not have to be stripped prior to the formation of the pad oxide.
A still further object of the present invention is to provide a process for preparing silicon wafers by utilizing a high temperature oxidation process that creates a denuded zone; adjust the precipitate density to a given target value; and provide a thin pad oxide layer for further processing.
In general, the invention process of providing silicon wafers is accomplished by adjusting the oxide thickness and the DZ depth to desired target values by controlling temperature and annealing time in 100% O
2
at high pressure close to atmospheric pressure.
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patent: 4314595 (1982-02-01), Yamamoto et al.
patent: 5242854 (1993-09-01), Solheim et al.
patent: 5360769 (1994-11-01), Thakur et al.
patent: 6100149 (2000-08-01), Nenyei et al.
patent: 6191010 (2001-02-01), Falster
Yao, et al., “High Quality Ultrathin Dielectric Film Grown on Silicon in a Nitric Oxide Ambient”, Applied Physics Letters, vol. 64, No. 26, pp. 3584-3586, Jun. 27, 1994.*
Wolf, S. and Tauber, R.N., Silicon Processing for the VLSI Era—vol. 1, pp. 216-217, 1986.
Gaertner Thomas
Schrems Martin
Tews Helmut Horst
Braden Stahton
Novacek Christy
Siemens Aktiengesellscharft
Trinh Michael
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