Combined logic gate and latch

Details Combined logic gate and latch Combined logic gate and latch

1996-08-05

1999-03-23

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 17, 326 98, 327219, H03K 19096, H03K 1900

Patent

active

058865411

ABSTRACT:
A circuit combines the functions of a logic gate and a latch to lower steady state power dissipation during gate operation. The circuit operates in two modes: a flow-through mode and a latched mode. In the flow-through mode, a gate portion which receives one or more digital input signals implements the complement of a desired Boolean logic function on the input signals and provides an internal signal. The gate portion may have a steady-state power dissipation while providing the internal signal. An inverter in a latch portion of the circuit inverts the internal signal to generate an output signal which represents the desired logical combination of the input signals. The inverter provides the output signal with a full-range CMOS voltage. In latched mode, the gate portion is disabled to stop the steady-state power dissipation while the latch portion of the circuit preserves the desired output signal.

REFERENCES:
patent: 4700086 (1987-10-01), Ling et al.
patent: 4972102 (1990-11-01), Reis et al.
patent: 5027012 (1991-06-01), Soeki et al.
patent: 5070262 (1991-12-01), Hashimoto

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