Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-04
2007-09-04
Chung, Phung My (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S733000, C714S738000
Reexamination Certificate
active
11166432
ABSTRACT:
A processor including a first distributed shift generator associated with a first time domain, wherein the first distributed shift generator is coupled to a first group of scan chains, the first distributed shift generator to send a shift-enable-flop signal to be received by the first group of scan chains. The processor including a second distributed shift generator associated with a second time domain, wherein the second distributed shift generator is coupled to a second group of scan chains, the second distributed shift generator to send a shift-enable-flop signal to be received by the second group of scan chains. The processor including a scan test controller coupled to the first and second distributed shift generators, the scan test controller to provide clocking signals for the first time domain and the second time domain for performing an at-speed test of circuits coupled to the first group of scan chains.
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Athavale Atul S.
Ng Jason R.
Blakely , Sokoloff, Taylor & Zafman LLP
Chung Phung My
Intel Corporation
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