Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2002-10-01
2004-08-24
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
06782502
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of integrated circuit testing.
2. Description of the Related Art
An integrated circuit (IC) is a miniature electric circuit containing large numbers of discrete electronic circuit elements, such as transistors, resistors, capacitors, and diodes, which are packaged as a single unit with leads extending from it for input, output, and power-supply connections. The electronic circuit elements are formed by selective manipulation of a single chip of semiconductor material, often in combination with various other semi-conducting and/or conducting materials.
It is common in the art to roughly classify integrated circuits dependent upon their transistor density. Presently, there are effectively four common integrated circuit classifications: small-scale integrated circuits (SSIs); medium-scale integrated circuits (MSIs); large-scale integrated circuits (LSIs); and very-large-scale integrated circuit (VLSIs). Exactly what transistor densities constitute the various “classes” varies, but at present SSIs typically include up to several tens of transistors, MSIs include from many tens to several hundred transistors; LSIs include from several hundred to a few thousand transistors; and VLSIs several hundred thousand or more. Most ICs in use today would constitute VLSIs.
One powerful feature of integrated circuits is the ability to use such integrated circuits to produce several levels of abstraction, which is useful for complete design. For example, integrated circuit design can be viewed at one level of abstraction in terms of discrete electronic circuit components (e.g., resistors, capacitors, inductors, transistors, diodes, etc.). Integrated circuit design can also be viewed at a next-higher layer of abstraction in terms of logic diagrams consisting of well-defined digital Boolean logic circuits such as AND, NAND, OR, and NOR gates, where each such gate consists of well-defined congeries of the discrete electronic circuit elements. Integrated circuit design can also be viewed at yet a next-higher layer of abstraction known as Register Transfer Level (RTL), which consists of program-like statements describing the movement or processing of data between storage elements. Integrated circuits can also be viewed at a yet again higher layer of abstraction known as a functional block diagram layer, which shows the major subcomponents of a design. This is the level at which the highest conceptual design work is done.
Typically, IC design is done at the functional block diagram, RTL, and logic diagram levels. It is common for whole teams of people (and sometimes whole companies) to focus on various aspects of the design at various abstraction levels. However, as noted, the design process rarely proceeds at a lower level than that of logic diagrams. Below this level, it is common to program the desired logic diagram layouts into artificially intelligent software, which automatically produces discrete circuit component level diagrams to be enacted within the integrated circuit.
As noted above, the discrete circuit level components are produced via the selective manipulation of a single piece of semiconductor material, where such selective manipulation usually includes the use of other semi-conducting and/or conducting materials. The discrete circuit level components are created via this selective manipulation.
The regions affected by the selective manipulation of the single piece of semiconductor material are almost unimaginably small. For example, current VLSI production procedures produce the discrete circuit components by manipulating material by use of sub-micron width (i.e., widths of less that ({fraction (1/1,000,000)}) of a meter) lines drawn, or “etched,” in the semiconductor material. Furthermore, the sizes of the regions manipulated decrease virtually every week.
Due to the very small regions manipulated during VLSI production, errors invariably occur. This can be the result of contamination of the material, or minor variations in the length, width, or height of lines etched. These errors in production often result in errors in the behavior of the discrete electronic circuit level components.
As noted, the higher abstraction logic diagram level is designed using logic diagram level component circuits consisting of congeries of discrete circuit level components. Consequently, errors in production sufficient to produce errors in the behavior of the discrete circuit level components can “propagate” upwards to the logic diagram level since the logic diagram circuits are built from congeries of these malfunctioning circuit components. If the errors are severe, then such malfunctioning will be very apparent in that the affected logic diagram level circuits will not function. However, if the malfunction is not severe, it is possible that the affected logic diagram level components will perform, but will perform in such a way that is out of design tolerances, which can cause a general system malfunction or failure as these logic diagram level errors “propagate” up the abstraction-layer hierarchy to affect the RTL and functional block diagram level designs.
A principle way in which such a malfunction will manifest at the logic diagram level is that one or more of the logic diagram level circuits will perform their functions appropriately, but so slowly that they affect the design. Accordingly, testing has been devised in the art to ensure that the logic diagram level circuits are performing their functions within design tolerances. This testing basically amounts to the following: (1) defining at least one combinational logic path through a combinational logic circuit; (2) initializing the combinational logic circuit with a given set of inputs; (3) waiting until the combinational logic circuit becomes stable; (4) changing the logic levels of one or more of the set of inputs; and (5) and measuring the time it takes for output of the combinational logic circuit at the end of the defined path to change subsequent to the change in the set of inputs. This testing is illustrated at a basic conceptual level with reference to
FIGS. 1A
,
1
B and
1
C.
With reference now to
FIGS. 1A
,
1
B, and
1
C, shown is combinational logic circuit
100
composed of logic diagram level circuits
108
,
110
which will be utilized to illustrate how delay testing of combinational logic diagram circuits is achieved in the related art. The diagrams in
FIGS. 1A
,
1
B, and
1
C show a combinational logic path that implements the equation output signal Z=(input signal a*input signal b)+input signal c, with the path from input signal a to output signal Z, whose delay is to be measured, illustrated by the heavier dark line segments of path
102
,
104
,
106
. As described above, two input signal test patterns are needed to measure the delay path: a first input signal test pattern to initialize output signal Z, and a second input signal test pattern to cause a change in output signal Z from that to which it was previously initialized.
Depicted is that feeding combinational logic circuit
100
is scan chain register bank
101
composed of Registers a, b, and c. As has been discussed, scan chain test patterns need to be utilized to test the delay associated with path
102
,
104
,
106
. Such scan chain test patterns are typically generated by recognizing that the various logic circuits providing inputs to the path whose delay is to be tested generate certain requirements relevant to such scan chain patterns. For example, regarding AND gate
108
, in the context of controlling the value of output Z, those skilled in the art will recognize that a non-controlling logic value is logic 1. Furthermore, those skilled in the art will also recognize that, in the context of controlling of output Z, a non-controlling value is logic 0 for OR gate
110
. Consequently, to test the delay of path
102
,
104
,
106
both input signals from Register b and input signal from Register c should stay at non-controlling values, while input signal
Lamarre Guy J.
NEC Electronics Inc.
Skjerven Morrill LLP
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