Combinational circuit, and encoder, decoder and...

Details Combinational circuit, and encoder, decoder and... Combinational circuit, and encoder, decoder and...

2006-03-07

2006-03-07

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S781000, C708S492000

Reexamination Certificate

active

07010738

ABSTRACT:
A combinational circuit comprises: a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2m) (m is an integer equal to or greater than 2), wherein the multipliers include an input side XOR calculator, an AND calculator, and an output side XOR calculator, and wherein the multipliers share the input side XOR calculator. Further, according to the present invention, these multipliers each include an adder connected between an AND calculator and an output side XOR calculator, wherein the output side XOR calculator is used in common, and wherein the outputs of the AND calculators in the multipliers are added by the adders, and the addition results are calculated by the output side XOR calculator that is used in common.

REFERENCES:
patent: 5107503 (1992-04-01), Riggle et al.
patent: 6327654 (2001-12-01), Oowaki et al.
patent: 6718138 (2004-04-01), Sugawara

Affiliated with

Also associated with

Rating

Combinational circuit, and encoder, decoder and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Combinational circuit, and encoder, decoder and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Combinational circuit, and encoder, decoder and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3584859