Combination of non-lithographic shrink techniques and trim...

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

Reexamination Certificate

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Details

C430S322000, C430S030000, C430S330000, C430S320000, C356S636000, C356S637000, C356S625000, C356S601000

Reexamination Certificate

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07405032

ABSTRACT:
The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit.Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.

REFERENCES:
patent: 6561706 (2003-05-01), Singh et al.
patent: 6650422 (2003-11-01), Singh et al.
patent: 6730458 (2004-05-01), Kim et al.
patent: 6905949 (2005-06-01), Arita
patent: 7064846 (2006-06-01), Amblard et al.
patent: 7159205 (2007-01-01), Amblard et al.

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