Combination DRAM and SRAM memory array

Details Combination DRAM and SRAM memory array Combination DRAM and SRAM memory array

1991-12-23

1994-03-01

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523003, 36523005, G11C 700

Patent

active

052914445

ABSTRACT:
A combination dynamic random access memory (DRAM) and static random access memory (SRAM) (150) array, includes a plurality of DRAM sense amplifiers (82, 84), each coupled to at least one DRAM bitline (86), with a plurality of DRAM memory cells selectively coupled to each of the bitlines (86). The sense amplifiers (82, 84) are organized into groups, with each group of sense amplifiers (82, 84), selectively coupled to respective true and complement I/O lines (102, 104). For each pair of the true and complement I/O lines (102, 104), an SRAM latch (150) is coupled to the pair.

REFERENCES:
patent: 4905195 (1990-02-01), Fukuda et al.
patent: 5016224 (1991-05-01), Tanaka et al.
patent: 5029134 (1991-07-01), Watanabe
patent: 5138577 (1992-08-01), Oh

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