Column switch in memory device and cache memory using the same

Details Column switch in memory device and cache memory using the same Column switch in memory device and cache memory using the same

2001-01-25

2003-02-04

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

C365S049130, C365S189070, C365S207000, C365S208000

Reexamination Certificate

active

06515916

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a column switch in a memory device having a logic calculation function used at reading tag memory data of a cache memory and a cache memory using the same.
2. Description of the Related Art
In a computer and other data processing apparatus including a central processing unit (CPU) and a main memory, a cache memory is provided separately from the main memory and able to be accessed at a high speed. When the main memory in the CPU is accessed, accessed data and tag data relating to an address information of the data are temporarily stored in the cache memory. When the CPU again accesses data stored at the same address in the main memory next time, the data stored in the cache memory is output to the CPU instead of that stored in the main memory. Therefore, by using the cache memory, data accessing at a high speed can be realized when repeatedly accessing to data in the same memory area in the main memory, and currently, most computers are provided with cache memories. Also, an IC chip wherein a CPU and cache memory are integrated on the same semiconductor chip has become a product.
FIG. 1
is a view of an example of the configuration of a data processing apparatus including a cache memory. As shown in the figure, the data processing apparatus is comprised of a CPU
10
, a main memory
20
and a cache memory
30
. A memory access, for example, reading data from the main memory is performed via a data but
40
and an address bus
50
. The CPU
10
outputs an address signal ADR to the main memory
20
via the address bus
50
, data stored at an address specified by the address signal ADR is read and transferred to the CPU
10
via the data bus.
At the same time with the above reading, the read data and a part of the address signal ADR relating thereto (for example, upper n bits in the m-bit address signal ADR, hereinafter, it is referred to as ADRa. Here, m and n are natural numbers and m>n.) are written in the cache memory
30
. When the CPU reads data at the same address as the previous time from the main memory
20
, data stored in the cache memory is read instead of that in the main memory
20
and supplied to the CPU
10
. Since the cache memory
30
is comprised for example of an SRAM able to be accessed at a high speed, data reading at a higher speed can be realized compared with the main memory.
FIG. 2
is a view of an example of the configuration of the cache memory
30
. As shown in the figure, the cache memory
30
is comprised of a cache control circuit
31
, a tag memory
32
, a data memory
33
, a tag data reading circuit
34
and a hit signal generation circuit
35
. Note that
FIG. 2
is a simplified view showing only a portion relating to data reading in the cache memory
30
. In an actual cache memory, partial circuits, such as a writing circuit for storing data, a data reading circuit for reading data from the data memory
33
at the time of hitting, etc., are included in the tag memory
32
and data memory
33
, respectively, but they will be omitted here.
The cache control circuit
31
respectively controls writing and reading of data in the tag memory
32
and data memory
33
. The tag memory
31
stores address information relating to data stored in the data memory
33
(hereinafter, referred to as tag data). Namely, when reading data from the main memory
20
, reading data is stored in the data memory
33
and tag data relating to the reading data is stored in the tag memory
32
.
The tag data reading circuit
34
reads the tag data TGD stored in the tag memory
32
and outputs to the hit signal generation circuit
35
.
The hit signal generation circuit
35
compares the tag data TGD read by the tag reading circuit
34
and the address ADRa from the CPU
10
and outputs a hit signal S
hit
when the tag data TGD matches the address ADRa.
The cache control circuit
31
, when receiving the hit signal S
hit
from the hit signal generation circuit
35
, outputs a control signal SC to a not shown data reading circuit, reads data from the data memory
32
by the data reading circuit and outputs the same to the data bus
40
.
With the provision of above mentioned cache memory
30
, a high speed accessing can be realized and performance of the data processing apparatus can be improved without using any costly high speed memory as a main memory.
In the above cache memory of the related art, however, the tag data reading circuit
34
reads tag data from the tag memory
32
and a comparison circuit compares so as to generate a bit signal S
hit
. The comparison circuit is comprised, for example, of an exclusive OR (XOR) circuit. A logic circuit performing XOR calculation is normally not capable of directly processing a weak read signal output from the tag memory, thus, the tag data reading circuit
34
amplifies the read signal by a sense amplifier to convert to have a sufficient amplitude level so that the logic circuit can perform processing and input the same to the logic circuit. The logic circuit for performing XOR calculation is comprised, for example, of a CMOS circuit and calculates a signal of a CMOS level, therefore, there arises a disadvantage that the processing speed declines due to dealing with a signal having a large amplitude and a generation speed of the hit signal declines.
FIG. 3
is a view of a partial circuit of the cache memory including a cache control circuit
31
, tag memory
32
, tag data reading circuit
34
and a hit signal generation circuit
35
. As shown in the figure, the tag data reading circuit
34
is comprised of a row decoder
301
, column decoder
302
, a column switch
303
, sense amplifier
304
, a level conversion circuit
305
and an exclusive OR circuit
306
.
The tag memory
32
is a memory cell array comprised, for example, of a plurality of memory cells arranged in a matrix. Memory cells of the respective rows are connected to a plurality of word lines and memory cells of the respective columns are connected to a plurality of bit lines. The word lines and bit lines are selected by the row decoder
301
and the column decoder
302
. Note that the row decoder
301
and the column decoder
302
are controlled by the cache control circuit
31
.
The reading from the tag memory
32
is performed on a memory cell connected to a bit line selected by the column decoder
302
among the memory cells connected to the word lines selected by the row decoder
301
. The column decoder
302
controls the column switch
303
and a read signal on the selected bit line is transferred to the sense amplifier
304
. Stored data in the selected memory cell in the tag memory
32
is read in accordance with a voltage level of a read signal of the selected bit line by the sense amplifier
304
. The level conversion circuit
305
converts a level of an output signal of the sense amplifier
304
and provides the same to the exclusive OR circuit
36
. For example, assuming that the XOR circuit
306
is comprised by the CMOS circuit, the level conversion circuit
305
converts an amplitude level of the output signal of the sense amplifier
304
to be a CMOS level.
The XOR circuit
306
obtains an exclusive OR of every bit in the tag data from the level conversion circuit
305
and in the address signal ADRa input via the address bus, and outputs the results to the hit signal generation circuit
35
. The XOR circuit
306
compares the read tag data and an input address signal ADRa and provides the comparison result to the hit signal generation circuit
35
. The hit signal generation circuit
35
generates a hit signal S
hit
in accordance with matching or unmatching of the comparison result and supplies the same to the cache control circuit
31
.
As explained above, in the XOR circuit
306
used for comparison calculation of the tag data and the address signal ADRa, for example a signal of a CMOS level is dealt, so a weak signal output from the column switch
303
is amplified in the sense amplifier
304
, converted by the level conversion circuit
305
, and then, sup

Affiliated with

Also associated with

Rating

Column switch in memory device and cache memory using the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Column switch in memory device and cache memory using the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Column switch in memory device and cache memory using the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3118156