Column selection circuit

Details Column selection circuit Column selection circuit

1998-07-31

1999-04-06

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Precharge

365205, 365207, 365208, G11C 700

Patent

active

058927220

ABSTRACT:
A column selection circuit is disclosed, in which a layout area is minimized by reducing the number of data bus lines and sensing speed characteristic is improved by reducing sensing time of a bit line. In a memory for transmitting data stored in a memory cell to a main sensing amplifier through a bit line and a bit bar line and storing the data output from the main sensing amplifier in the memory cell through the bit line and the bit bar line, the column selection circuit includes an equalizer for equalizing the bit line and the bit bar line, a bit line sensing amplifier for compensating signal voltage levels of the bit line and the bit bar line as a word line is selected, first and second enable signal output portions for outputting enable signals to operate the bit line sensing amplifier, a data bus line and a data bus bar line for transmitting the data transmitted to the bit line and the bit bar line from the memory cell to the main sensing amplifier, and transmitting the data output from the main sensing amplifier to the bit line and the bit bar line, a data transmission portion for selectively transmitting the data of the data bus line and data bus bar line and the data of the bit line and bit bar line between the respective lines in response to a column selection signal, a control signal for reading and a write enable signal, and a precharge level adjusting portion for adjusting precharge level of the data bus line and the data bus bar line.

REFERENCES:
patent: 4984206 (1991-01-01), Komatsu et al.
patent: 5323349 (1994-06-01), Hamade et al.
patent: 5539279 (1996-07-01), Takeuchi et al.
Taguchi, et al, "A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture", IEEE Journal of Solid-State Circuits, vol., 26, No. 11, Nov. 1991, pp. 1493-1497.

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