Column selecting circuit in semiconductor memory device

Details Column selecting circuit in semiconductor memory device Column selecting circuit in semiconductor memory device

1996-05-23

1999-02-09

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

36523003, 36523006, 36523008, 36523001, G11C 700

Patent

active

RE0360899

ABSTRACT:
Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

REFERENCES:
patent: 4429374 (1984-01-01), Tanimura
patent: 4855957 (1989-08-01), Nogami
patent: 5040152 (1991-08-01), Voss et al.
patent: 5210723 (1993-05-01), Bates et al.
patent: 5315548 (1994-05-01), Ooishi
"An Experimental 16Mb CMOS DRAM Chip with a 100 MHz Serial Read/Write Mode", Shigeyoshi Watanabe et al., 1988 IEEE International Solid State Circuits Conference, Feb. 1988, pp. 248-249.

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