Column select line control circuit for synchronous semiconductor

Details Column select line control circuit for synchronous semiconductor Column select line control circuit for synchronous semiconductor

1998-12-28

2000-05-16

Dinh, Son T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365210, 365233, G11C 800

Patent

active

060646225

ABSTRACT:
A synchronous memory includes a column main-decoder circuit that is directly coupled to column select lines (CSL), and a timing controller that controls both enable timing and disable timing of the column select lines by controlling the column pre-decoder. The CSL timing controller generates a CSL timing control signal representative of the enable timing and the disable timing of the column select lines. The column pre-decoder is either enabled or disabled depending upon logic states of the CSL timing control signal. The timing controller includes a first control circuit which provides a CSL enable control signal, a CSL disable control circuit which provides a CSL disable control signal, and a flip-flop circuit which receives the CSL enable and disable control signals and provides the CSL timing control signal.

REFERENCES:
patent: 5629903 (1997-05-01), Agata
patent: 5790470 (1998-08-01), Yonaga
patent: 5898637 (1999-04-01), Lakhani et al.
patent: 5933376 (1999-08-01), Lee

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