Column/row redundancy architecture using latches programmed...

Details Column/row redundancy architecture using latches programmed... Column/row redundancy architecture using latches programmed...

2006-10-10

2006-10-10

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S230030, C365S189050, C365S230080

Reexamination Certificate

active

07120068

ABSTRACT:
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.

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