Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-10-05
2003-04-22
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230060, C365S230020
Reexamination Certificate
active
06552938
ABSTRACT:
BACKGROUND
The present invention relates generally to integrated circuit memory devices and, more particularly, to a column redundancy system and method for embedded dram (eDRAM) devices with multibanking capability.
The discarding or scrapping of defective integrated circuits when defects are identified is economically undesirable, particularly if only a small number of circuit elements are actually defective. In addition, relying on a “zero defect” goal in the fabrication of integrated circuits is an unrealistic expectation from a practical standpoint. Accordingly, redundant circuit elements are provided on integrated circuits to reduce the number of discarded integrated circuits. If a primary circuit element is determined to be defective during testing, a redundant circuit element is substituted for the defective primary circuit element. Substantial reductions in scrapped devices may be achieved by using redundant circuit elements without substantially increasing the cost of the integrated circuit.
One example of a type of integrated circuit device that uses redundant circuit elements is integrated memory circuits, such as dynamic random access memories (DRAMs). These devices typically include millions of individual memory cells arranged in arrays of addressable rows and columns. The rows and columns of memory cells are the primary circuit elements of the integrated memory circuit. By providing redundant circuit elements, either as rows or columns, defective primary rows or columns can be replaced.
Because the individual primary circuit elements (rows or columns) of an integrated memory circuit are separately addressable, replacing a defective circuit element typically involves blowing fuse-type devices in order to “program” a redundant circuit element to respond to the address of the defective primary circuit element. This process is very effective for permanently replacing defective primary circuit elements. In the case of DRAMs, for example, a particular memory cell is selected by first providing a unique row address corresponding to the row in which the particular memory cell is located and subsequently providing a unique column address corresponding to the column in which the particular memory cell is located. When the address of the defective primary circuit element is presented by the memory customer (user), the redundancy circuitry must recognize this address and thereafter reroute all signals to the redundant circuit element.
As new and improved memory products are developed (e.g., embedded DRAM with multibanking capability), the speed of a column redundancy system should correspondingly “keep up” with the speed of the new designs. In other words, it is undesirable to have a column redundancy system either negate or limit the performance of a data path as data is moved in and out of a memory array.
BRIEF SUMMARY
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a column redundancy system for a memory array having a page structure organized into columns and data lines. In an exemplary embodiment of the invention, the system includes a steering logic network for coupling a memory input/output (I/O) device to the memory array. A storage register is in communication with the steering logic network, the storage register for storing location information for defective data lines in the memory array. During a memory operation, the location information stored in the storage register is transmitted to the steering logic network, the storage register further having the location information loaded therein prior to the memory operation. Thereby, the steering logic network prevents any of the defective data lines from being coupled to the I/O device.
In a preferred embodiment, the location information is generated by programming programmable fuse devices included in the memory array, and the defective memory element location is decoded from a binary signal representation to a thermometric signal representation. The steering logic includes a series of multiplexing devices therein, the multiplexing devices capable of selectively routing the data lines in the memory array to corresponding data lines in the I/O device. If a first defective data line is detected in the memory array, then the steering logic prevents the first defective data line from being coupled to its corresponding data line in the I/O device. Furthermore, data lines subsequent to the first defective data line in the memory array are coupled by the steering logic to corresponding data lines in the I/O device in accordance with a one position shift.
If a second defective data line is detected in the memory array, then the steering logic prevents the second defective data line from being coupled to its corresponding data line in the I/O device. Then, data lines subsequent to the second defective data line in the memory array are coupled to corresponding data lines in the I/O device in accordance with a two position shift.
The column redundancy system preferably further includes carrying logic coupled with the storage register, the storage register further providing a first switching signal to the steering logic network and the carrying logic providing a second switching signal to the steering logic network. The first and second switching signals determine whether a data line in the memory array is connected in a first, second or third position with respect to a corresponding data line in the I/O device.
REFERENCES:
patent: 5673227 (1997-09-01), Engles et al.
patent: 5796662 (1998-08-01), Kalter et al.
patent: 6055204 (2000-04-01), Bosshart
patent: 6160302 (2000-12-01), Palagonia
Anand Darren L.
Barth, Jr. John E.
Cantor & Colburn LLP
Cioffi James
International Business Machines - Corporation
Le Thong
Nelms David
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