Column redundancy scheme for non-volatile flash memory using...

Details Column redundancy scheme for non-volatile flash memory using... Column redundancy scheme for non-volatile flash memory using...

2006-08-08

2006-08-08

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S189020, C365S189120, C365S189050

Reexamination Certificate

active

07088627

ABSTRACT:
A JTAG-programmable IC includes a memory array having redundant columns, a partial-width data register, and a full-width bitline register. A programming bitstream is shifted into the data register in discrete portions, with each portion being loaded into the bitline latch before the next portion is shifted into the data register. The programming bitstream portions fill the bitline latch sequentially unless a count indicator for a particular portion matches a predetermined defective column value, in which case that bitstream portion is rerouted to a region of the bitline latch associated with the redundant columns of the memory array. The count indicator is incremented with each new bitstream portion shifted into the data register. Once the programming bitstream is fully loaded into the bitline latch, the data is programmed into a selected row of the memory array in page mode.

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patent: 6816420 (2004-11-01), Liu et al.
Institute of Electrical and Electronics Engineering, Inc., “IEEE Standard Test Access Port and Boundary-Scan Architecture” IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993), Oct. 21, 1993, pp. 1-172, ISBN 1-55937-350-4, available from Institute of Electrical and Electronics Engineering, Inc., 345 East 47th Street, New York, NY 10017-2394.

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