Column redundancy of a multiple block memory architecture

Details Column redundancy of a multiple block memory architecture Column redundancy of a multiple block memory architecture

1995-07-31

1997-03-04

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Bad bit

36518902, 3652257, 36523002, 36523003, G11C 700

Patent

active

056086784

ABSTRACT:
According to the present invention, column redundancy circuitry provides column redundancy to an integrated circuit memory device having a multiple block memory architecture with limited programming overhead and maximum flexibility. Column redundancy circuitry is placed within a block of the multiple block memory architecture and may be placed within multiple blocks of the integrated circuit device as required. The column redundancy circuitry has a column select multiplexing circuit, an input/output select circuit for a redundant column of the memory array, and a redundant column select circuit to drive the input/output select circuit for a redundant column. Fuse circuitry contained within column select multiplexing circuit disables a bad prime column by removing fuses in order to isolate the bitline pair associated with the bad column from the read and write busses of the memory array. A fuse of an input/output select circuit contained within an input/output group of a block containing the redundant column to be enabled is left intact in order to connect the bitline pair of the enabled redundant column to the read and write busses of the memory array. The fuses of other input/output select circuits contained within the remaining input/output groups of the block are removed in order to isolate the redundant column from the write and read busses of the other input/output groups. The state of a redundant column signal of the input/output select circuit and whether the fuse is intact or removed will determine whether a redundant column is accessed. Control of the redundant column signal is provided by the redundant column select circuit; thus the redundant column select circuit drives the input/output select circuit for a redundant column.

REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 5355340 (1994-10-01), Coker et al.
patent: 5404331 (1995-04-01), McClure
patent: 5438546 (1995-08-01), Ishac et al.
patent: 5469391 (1995-11-01), Haraguchi

Affiliated with

Also associated with

Rating

Column redundancy of a multiple block memory architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Column redundancy of a multiple block memory architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Column redundancy of a multiple block memory architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2152037