Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-07-25
2002-01-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S210130, C365S230060
Reexamination Certificate
active
06343037
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a column redundancy circuit for semiconductor memory, and in particular to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency, by selecting and outputting one of a normal data or a redundancy data which are outputted from the memory array, according to a row address and a column address.
2. Discussion of the Background Art
FIG. 1
is a block diagram illustrating the conventional column redundancy circuit using the column address.
A clock buffer
1
buffers an external clock signal EX_CLK and outputs it to a pulse width control unit
5
. An address buffer
2
buffers an external address EX_ADD and outputs it to a column redundancy unit
4
and a column predecoder
6
. In a burst mode, an address counter
3
counts the buffered external address EX_ADD, and outputs an internal address IN_ADD to the column redundancy unit
4
and the column predecoder
6
. The column redundancy unit
4
determines whether to repair each memory array unit according to the external address EX_ADD and the internal address IN_ADD to be inputted to the column redundancy unit
4
, and outputs corresponding redundancy information RE_INF. The pulse width control unit
5
serves to output the internal clock signal EX_CLK to the column predecoder
6
for determining a pulse width of a column selecting signal according to the buffered external clock signal EX_CLK, and to output a redundancy clock signal CLK_RE_INF having the redundancy information RE_INF to a column decoder
7
.
The column predecoder
6
enables a normal address path in a non-redundancy mode where a repair operation is not performed. To the contrary, the column predecoder
6
disables the normal address path in a redundancy mode where the repair operation is carried out, predecodes a column address Y_ADD from the address buffer
2
, and outputs it to the column decoder
7
. A pulse width of the predecoded column address Y_ADD is determined by the external clock signal EX_CLK.
The column decoder
7
determines whether to repair according to the redundancy clock signal CLK_RE_INF, and outputs a normal column selecting signal NYS or a redundancy column selecting signal RYS to a memory array
8
. That is, the column decoder
7
outputs the normal column selecting signal NYS in the non-redundancy mode, and outputs the redundancy column selecting signal RYS in the redundancy mode. Here, the normal column selecting signal NYS and the redundancy column selecting signal RYS are signals for selecting a sense amplifier (not shown) in the memory array
8
.
The memory array
8
consists of a plurality of normal memory cells and a plurality of redundancy memory cells. When the column decoder
7
outputs the normal column selecting signal NYS, the data stored in the normal memory cells of the memory array are read. In case the column decoder
7
outputs the redundancy column selecting signal RYS, the data stored in the redundancy memory cells of the memory array
8
are read. The data which have been read are-inputted to a main amplifier
9
via an input/output line LIOT/B, amplified and outputted to an output buffer (not shown).
FIGS. 2A and 2B
are timing diagrams for the circuit in FIG.
1
.
FIG. 2A
is a timing diagram in the non-redundancy mode, and
FIG. 2B
is a timing diagram in the redundancy mode. As shown in the Figures, if a column address strobe signal CAS is inputted in a state where the external clock signal EX_CLK is inputted, the external address EX_ADD and the internal address IN_ADD are transited. When a first predetermined time t1 lapses after the internal address IN_ADD is transited, the redundancy information RE_INF is at a high level, and the redundancy clock signal EX_CLK is also at a high level. As shown in
FIG. 2A
, the redundancy clock signal EX_CLK being at a high level implies that the column redundancy circuit is operated in the non-redundancy mode. In
FIG. 2B
, the redundancy clock signal EX_CLK being at a high level means that the column redundancy circuit is operated in the redundancy mode.
When a second predetermined time t2 lapses after the first predetermined time t1, the normal column selecting signal NYS is enabled in the normal mode, as shown in
FIG. 2A
, and the redundancy column selecting signal RYS is enabled in the redundancy mode, as depicted in FIG.
2
B.
The second predetermined time t2 is a time taken to determine whether the column predecoder
6
and the column decoder
7
operate the column redundancy circuit in the normal mode or the redundancy mode according to whether to repair, and is identical in the normal mode and the redundancy mode.
The second predetermined time t2 is clearly longer when the normal column selecting signal NYS is outputted without determining whether to repair. As the second predetermined time t2 becomes longer, a total processing speed of the column redundancy circuit is reduced.
In order to overcome such a disadvantage,
FIG. 3
illustrates a block diagram of another conventional redundancy circuit. As shown in Figures, the clock buffer
1
, the address buffer
2
and the address counter
3
are identical in constitution and operation to those in
FIG. 1. A
pulse width control unit
31
outputs an internal clock signal IN_CLK to a column predecoder
32
for determining a pulse width of a column selecting signal according to a buffered external clock signal EX_CLK. A column address Y_ADD is inputted to a column decoder
33
via the address buffer
2
and the column predecoder
32
. The column decoder
33
outputs a column selecting signal YS to the memory array
34
. Here, the column address Y_ADD and the column selecting signal YS are not related to a repair operation. The memory array
34
includes normal memory cells and redundancy memory cells. Each array is not divided into a plurality of array units, differently from the memory array
8
as illustrated in FIG.
1
. The data stored in the normal array cells are inputted to a main amplifier
35
through a normal input/output line NLIOT/B, and the data stored in the redundancy memory cells are inputted to the main amplifier
35
via a redundancy input/output line RLIOT/B.
The column redundancy unit
36
determines whether to repair the normal input/output line NLIOT/B and the redundancy input/output line RLIOT/B, and outputs redundancy information RE_INF to the main amplifier
35
. According to the redundancy information RE_INF, the main amplifier
35
amplifies and outputs one of the data inputted through the normal input/output line NLIOT/B or the redundancy input/output line RLIOT/B.
As described above, in the circuit as shown in
FIG. 3
, when the column selecting signal YS (identical to the normal column selecting signal NYS as shown in
FIG. 1
) is outputted to the memory array
34
, whether to repair or not is determined, differently from the circuit as shown in FIG.
1
. Accordingly, an extra amount of time to determine whether to repair is not necessary. As a result, the circuit in
FIG. 3
is faster in operation than the circuit in FIG.
1
. However, the memory array is not divided, and thus redundancy efficiency is reduced. In addition, as the memory array is divided into a plurality of array units, and thus the number of the array units is increased, a load of the redundancy input/output line RLIOT/B is also increased. Accordingly, in order to employ such a circuit, the number of the array units must be limited. Thus, it is not suitable for a high integration circuit where the memory array is divided into many array units.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the present invention to provide a column redundancy circuit for a semiconductor memory which can improve an operational speed of a high integration semiconductor circuit whose memory array is divided into a plurality of memory array units.
It is another object of the present invent
Kim Ju Han
Park San Ha
Pyeon Hong Beom
Hyundai Electronics Industries Co,. Ltd.
Le Thong
Morgan & Lewis & Bockius, LLP
Nelms David
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