Column redundancy circuit for CMOS dynamic random access memory

Details Column redundancy circuit for CMOS dynamic random access memory Column redundancy circuit for CMOS dynamic random access memory

1987-08-21

1989-05-09

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 700

Patent

active

048294802

ABSTRACT:
A dynamic random access memory for substituting a normal column line coupled for faulty normal memory cells for a spare column line coupled to defect-free spare memory cells with a latch having a master fuse and an input terminal coupled to a reset clock, a spare column decoder enabling or disabling the spare column line with the output of the latch and the selective input of either true column address signals or complement column address signals and a plurality of normal column decoders enabling or disenabling normal column lines with the column address signals addressing a specified normal column line under the control of the ouptut of the spare column decoder.

REFERENCES:
patent: 4228528 (1979-02-01), Cenker et al.
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 4556975 (1985-12-01), Smith et al.
patent: 4734889 (1988-03-01), Mashiko et al.

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