Column redundancy circuit for a semiconductor memory device

Details Column redundancy circuit for a semiconductor memory device Column redundancy circuit for a semiconductor memory device

1996-10-02

1998-09-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 3652257, 36523002, G11C 700

Patent

active

058124667

ABSTRACT:
The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line. The column redundancy circuit includes: transmitting means comprised of the data input/output lines for transmitting the data of the memory cell; column decoder and input/output control circuits connected to the transmitting means and decoding a column address input to input data; a circuit connected to the transmitting means and outputting a given signal to the column decoder and input/output control circuits in response to a plurality of output signals output from fuses and a signal for controlling the transmitting means; a plurality of decoded fuse circuits, the levels of which are determined by one fuse connected to the circuit; multiplexers for selectively transmitting data from one of the data input/output lines to a specific data bus line among a plurality of data bus lines; and a decoding circuit which receives the outputs of the decoded fuse circuits and generates a redundancy signal.

REFERENCES:
patent: 5416740 (1995-05-01), Fujita et al.
patent: 5517450 (1996-05-01), Ohsawa
patent: 5548553 (1996-08-01), Cooper et al.
patent: 5576999 (1996-11-01), Kim et al.
patent: 5612917 (1997-03-01), Kozaru et al.

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