Column redundancy architecture for a read/write memory

Details Column redundancy architecture for a read/write memory Column redundancy architecture for a read/write memory

1992-01-31

1993-10-26

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523002, 36523006, 307449, 307463, G11C 700

Patent

active

052572293

ABSTRACT:
An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder, associated with each column. A plurality of redundant sense amplifiers are each associated with selected redundant columns. Each of the redundant column decoders includes a set of fuses for storing the column address responsive to which its associated redundant column is to be selected. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each redundant column decoder corresponding thereto, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

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