Column decoder for a semiconductor memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36523008, 365233, G11C 800

Patent

active

057779430

ABSTRACT:
A column decoder for a semiconductor memory device capable of a high-speed data access, such as in a synchronous memory. The column decoder receives and decodes a column address signal and produces a column select signal for driving a corresponding column select gate in accordance with the result of decoding. The column decoder includes a pre-decoder composed of a first pre-decoding section for pre-decoding the column address signal and producing at least one asynchronous pre-decoded signal, and a second pre-decoding section for pre-decoding the column address signal in response to a clock signal and producing at least one synchronous pre-decoded signal and enable signal; and a main decoder for producing at least one column select signal which is activated in response to the enable signal and is de-activated in response to a combination of the synchronous and asynchronous pre-decoded signals.

REFERENCES:
patent: 4931998 (1990-06-01), Ootani et al.
patent: 5233565 (1993-08-01), Wang
patent: 5428577 (1995-06-01), Yumitori et al.
patent: 5579268 (1996-11-01), Seo et al.
patent: 5586080 (1996-12-01), Raad et al.

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