Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2005-01-25
2005-01-25
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S218000, C711S219000, C711S220000
Reexamination Certificate
active
06848040
ABSTRACT:
Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address. The adder logic circuit processes the column address bits at the same time the address bits are being coupled through the second multiplexer to the first multiplexer as a function of the correct relationship between the internal address bits and the external address bits.
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Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen T
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