Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-24
2006-10-24
Kim, Matthew (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S122000, C711S123000, C711S141000, C711S144000, C711S173000, C711S147000, C711S148000, C711S170000, C718S100000, C718S102000, C718S107000
Reexamination Certificate
active
07127561
ABSTRACT:
Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.
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Crossland James B.
Hill David L.
Kaushik Shiv
Koufaty David A.
Marr Deborah T.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Matthew
Li Zhuo H.
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