Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-05-02
2006-05-02
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07039847
ABSTRACT:
A coding-decoding device and a coding-decoding method that take less time for coding and decoding are provided while using less number of logic gates. A memory device15substantially stores b pieces of conversion logic equations produced with a conversion logic equation producing device13. An operation device17has a programmable hardware logic circuit to constitute logics sequentially according to plural execution unit logic equations obtained by dividing b pieces of conversion logic equations stored in the memory device15into execution units for respective execution unit logic equations using the hardware logic circuit. Besides, the operation device17sequentially divides and calculates the second sentences from the first sentences according to the constituted logics. An output device19collects and outputs the second sentences calculated with the operation device17.
REFERENCES:
patent: 4833471 (1989-05-01), Tokuume et al.
patent: 6278748 (2001-08-01), Fu et al.
Fujimori Yoshikazu
Koyama Shinzo
Nozawa Hiroshi
Takayama Masao
Hogan & Hartson LLP
Kerveros James C.
Lamarre Guy
Rohm & Co., Ltd.
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